Sam Crow 6e3e964c12 cleanup net_spice docstrings

2023-07-19 12:45:41 -07:00

..

__init__.py

Verilog ROM model created for testing

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channel_route.py

Update copyright year

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contact.py

remove pins overwrite from contact class

2023-07-18 16:12:42 -07:00

delay_data.py

Update copyright year

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design.py

Merge branch 'char' into STA-refactor

2023-07-19 12:35:22 -07:00

errors.py

Update copyright year

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geometry.py

remove line ending whitespace from comment

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hierarchy_design.py

get connections from spice objects in instances

2023-07-18 10:50:50 -07:00

hierarchy_layout.py

fix pin/net dictionary deepcopy-ing

2023-07-18 16:14:38 -07:00

hierarchy_spice.py

cleanup net_spice docstrings

2023-07-19 12:45:41 -07:00

lef.py

implement pin_spice object

2023-07-13 16:45:05 -07:00

logical_effort.py

Update copyright year

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pin_layout.py

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power_data.py

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2023-01-28 22:56:27 -08:00

rom_verilog.py

Fixed formatting on all files

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route.py

Update copyright year

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timing_graph.py

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utils.py

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vector3d.py

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vector.py

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verilog.py

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wire_path.py

Update copyright year

2023-01-28 22:56:27 -08:00

wire_spice_model.py

add fixme note for unit conversion

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wire.py

Update copyright year

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