mirror of https://github.com/VLSIDA/OpenRAM.git
48 lines
1.2 KiB
Python
48 lines
1.2 KiB
Python
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class TextSection:
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def __init__(self, name, parent):
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self.name = name
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self.parent = parent
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self.lines = []
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self.sections = []
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self.sectionPos = []
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self.lineNum = 0
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self.repeat = 0
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def addLine(self, line):
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self.lines.append(line)
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self.lineNum+= 1
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def addSection(self, section):
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self.sections.append(section)
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self.sectionPos.append(self.lineNum)
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def expand(self):
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for i
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class VerilogTemplate:
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def __init__(self, template, output);
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self.template = template
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self.output = output
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self.sections = []
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def readTemplate(self):
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lines = []
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with open(self.template, 'r') as f:
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lines = f.readlines()
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currentSection = TextSection('base', None)
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for line in lines:
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if line[:2] == '#<':
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section = TextSection(line[2:], currentSection)
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currentSection.addSection(section)
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currentSection = section
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if line[:2] == '#>' and line[2:] == section.name:
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currentSection = currentSection.parent
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else:
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currentSection.addLine(line)
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