OpenRAM/compiler/modules
mrg e550d6ff10 Port name maps between bank and replica array working. 2019-07-15 11:29:29 -07:00
..
bank.py Port name maps between bank and replica array working. 2019-07-15 11:29:29 -07:00
bank_select.py Fix pnand2 height in bank select. Unsure how it passed before. 2019-07-03 15:12:22 -07:00
bitcell_array.py Port name maps between bank and replica array working. 2019-07-15 11:29:29 -07:00
control_logic.py Merge remote-tracking branch 'origin/dev' into rbl_revamp 2019-07-12 11:10:07 -07:00
delay_chain.py Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
dff.py Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
dff_array.py Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
dff_buf.py Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
dff_buf_array.py Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
dff_inv.py Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
dff_inv_array.py Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
dummy_array.py Port name maps between bank and replica array working. 2019-07-15 11:29:29 -07:00
hierarchical_decoder.py Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
hierarchical_predecode.py Fix space before comment 2019-06-14 08:43:41 -07:00
hierarchical_predecode2x4.py Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
hierarchical_predecode3x8.py Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
multibank.py Fix space before comment 2019-06-14 08:43:41 -07:00
port_address.py Correct wordline_driver enable to en, not en_bar. 2019-07-05 10:31:05 -07:00
port_data.py Port name maps between bank and replica array working. 2019-07-15 11:29:29 -07:00
precharge_array.py Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
replica_bitcell_array.py Port name maps between bank and replica array working. 2019-07-15 11:29:29 -07:00
replica_bitline.py Replica bitcell array with arbitrary RBLs working 2019-07-10 15:56:51 -07:00
replica_column.py Port name maps between bank and replica array working. 2019-07-15 11:29:29 -07:00
sense_amp.py Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
sense_amp_array.py Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
single_level_column_mux_array.py Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
tri_gate.py Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
tri_gate_array.py Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
wordline_driver.py Correct wordline_driver enable to en, not en_bar. 2019-07-05 10:31:05 -07:00
write_driver.py Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
write_driver_array.py Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00