mirror of https://github.com/VLSIDA/OpenRAM.git
330 lines
16 KiB
Python
330 lines
16 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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"""
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This file generates simple spice cards for simulation. There are
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various functions that can be be used to generate stimulus for other
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simulations as well.
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"""
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import tech
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import debug
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import subprocess
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import os
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import sys
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import numpy as np
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from globals import OPTS
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class stimuli():
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""" Class for providing stimuli functions """
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def __init__(self, stim_file, corner):
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self.vdd_name = "vdd"
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self.gnd_name = "gnd"
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self.pmos_name = tech.spice["pmos"]
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self.nmos_name = tech.spice["nmos"]
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self.tx_width = tech.drc["minwidth_tx"]
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self.tx_length = tech.drc["minlength_channel"]
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self.sf = stim_file
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(self.process, self.voltage, self.temperature) = corner
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try:
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self.device_libraries = tech.spice["fet_libraries"][self.process]
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except:
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debug.info(2, "Not using spice library")
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self.device_models = tech.spice["fet_models"][self.process]
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self.sram_name = "Xsram"
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def inst_sram(self, pins, inst_name):
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""" Function to instatiate an SRAM subckt. """
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self.sf.write("{} ".format(self.sram_name))
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for pin in self.sram_pins:
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self.sf.write("{0} ".format(pin))
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self.sf.write("{0}\n".format(inst_name))
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def inst_model(self, pins, model_name):
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""" Function to instantiate a generic model with a set of pins """
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self.sf.write("X{0} ".format(model_name))
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for pin in pins:
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self.sf.write("{0} ".format(pin))
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self.sf.write("{0}\n".format(model_name))
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def create_inverter(self, size=1, beta=2.5):
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""" Generates inverter for the top level signals (only for sim purposes) """
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self.sf.write(".SUBCKT test_inv in out {0} {1}\n".format(self.vdd_name, self.gnd_name))
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self.sf.write("mpinv out in {0} {0} {1} w={2}u l={3}u\n".format(self.vdd_name,
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self.pmos_name,
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beta * size * self.tx_width,
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self.tx_length))
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self.sf.write("mninv out in {0} {0} {1} w={2}u l={3}u\n".format(self.gnd_name,
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self.nmos_name,
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size * self.tx_width,
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self.tx_length))
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self.sf.write(".ENDS test_inv\n")
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def create_buffer(self, buffer_name, size=[1,3], beta=2.5):
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"""
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Generates buffer for top level signals (only for sim
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purposes). Size is pair for PMOS, NMOS width multiple.
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"""
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self.sf.write(".SUBCKT test_{2} in out {0} {1}\n".format(self.vdd_name,
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self.gnd_name,
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buffer_name))
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self.sf.write("mpinv1 out_inv in {0} {0} {1} w={2}u l={3}u\n".format(self.vdd_name,
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self.pmos_name,
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beta * size[0] * self.tx_width,
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self.tx_length))
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self.sf.write("mninv1 out_inv in {0} {0} {1} w={2}u l={3}u\n".format(self.gnd_name,
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self.nmos_name,
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size[0] * self.tx_width,
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self.tx_length))
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self.sf.write("mpinv2 out out_inv {0} {0} {1} w={2}u l={3}u\n".format(self.vdd_name,
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self.pmos_name,
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beta * size[1] * self.tx_width,
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self.tx_length))
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self.sf.write("mninv2 out out_inv {0} {0} {1} w={2}u l={3}u\n".format(self.gnd_name,
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self.nmos_name,
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size[1] * self.tx_width,
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self.tx_length))
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self.sf.write(".ENDS test_{0}\n\n".format(buffer_name))
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def gen_pulse(self, sig_name, v1, v2, offset, period, t_rise, t_fall):
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"""
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Generates a periodic signal with 50% duty cycle and slew rates. Period is measured
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from 50% to 50%.
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"""
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self.sf.write("* PULSE: period={0}\n".format(period))
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pulse_string="V{0} {0} 0 PULSE ({1} {2} {3}n {4}n {5}n {6}n {7}n)\n"
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self.sf.write(pulse_string.format(sig_name,
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v1,
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v2,
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offset,
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t_rise,
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t_fall,
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0.5*period-0.5*t_rise-0.5*t_fall,
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period))
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def gen_pwl(self, sig_name, clk_times, data_values, period, slew, setup):
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"""
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Generate a PWL stimulus given a signal name and data values at each period.
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Automatically creates slews and ensures each data occurs a setup before the clock
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edge. The first clk_time should be 0 and is the initial time that corresponds
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to the initial value.
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"""
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# the initial value is not a clock time
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debug.check(len(clk_times)==len(data_values),"Clock and data value lengths don't match. {0} clock values, {1} data values for {2}".format(len(clk_times), len(data_values), sig_name))
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# shift signal times earlier for setup time
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times = np.array(clk_times) - setup*period
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values = np.array(data_values) * self.voltage
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half_slew = 0.5 * slew
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self.sf.write("* (time, data): {}\n".format(list(zip(clk_times, data_values))))
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self.sf.write("V{0} {0} 0 PWL (0n {1}v ".format(sig_name, values[0]))
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for i in range(1,len(times)):
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self.sf.write("{0}n {1}v {2}n {3}v ".format(times[i]-half_slew,
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values[i-1],
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times[i]+half_slew,
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values[i]))
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self.sf.write(")\n")
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def gen_constant(self, sig_name, v_val):
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""" Generates a constant signal with reference voltage and the voltage value """
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self.sf.write("V{0} {0} 0 DC {1}\n".format(sig_name, v_val))
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def get_inverse_voltage(self, value):
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if value > 0.5*self.voltage:
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return 0
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elif value <= 0.5*self.voltage:
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return self.voltage
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else:
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debug.error("Invalid value to get an inverse of: {0}".format(value))
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def get_inverse_value(self, value):
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if value > 0.5:
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return 0
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elif value <= 0.5:
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return 1
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else:
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debug.error("Invalid value to get an inverse of: {0}".format(value))
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def gen_meas_delay(self, meas_name, trig_name, targ_name, trig_val, targ_val, trig_dir, targ_dir, trig_td, targ_td):
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""" Creates the .meas statement for the measurement of delay """
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measure_string=".meas tran {0} TRIG v({1}) VAL={2} {3}=1 TD={4}n TARG v({5}) VAL={6} {7}=1 TD={8}n\n\n"
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self.sf.write(measure_string.format(meas_name,
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trig_name,
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trig_val,
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trig_dir,
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trig_td,
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targ_name,
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targ_val,
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targ_dir,
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targ_td))
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def gen_meas_find_voltage(self, meas_name, trig_name, targ_name, trig_val, trig_dir, trig_td):
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""" Creates the .meas statement for the measurement of delay """
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measure_string=".meas tran {0} FIND v({1}) WHEN v({2})={3}v {4}=1 TD={5}n \n\n"
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self.sf.write(measure_string.format(meas_name,
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targ_name,
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trig_name,
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trig_val,
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trig_dir,
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trig_td))
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def gen_meas_find_voltage_at_time(self, meas_name, targ_name, time_at):
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""" Creates the .meas statement for voltage at time"""
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measure_string=".meas tran {0} FIND v({1}) AT={2}n \n\n"
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self.sf.write(measure_string.format(meas_name,
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targ_name,
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time_at))
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def gen_meas_power(self, meas_name, t_initial, t_final):
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""" Creates the .meas statement for the measurement of avg power """
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# power mea cmd is different in different spice:
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if OPTS.spice_name == "hspice":
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power_exp = "power"
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else:
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power_exp = "par('(-1*v(" + str(self.vdd_name) + ")*I(v" + str(self.vdd_name) + "))')"
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self.sf.write(".meas tran {0} avg {1} from={2}n to={3}n\n\n".format(meas_name,
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power_exp,
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t_initial,
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t_final))
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def gen_meas_value(self, meas_name, dout, t_intital, t_final):
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measure_string=".meas tran {0} AVG v({1}) FROM={2}n TO={3}n\n\n".format(meas_name, dout, t_intital, t_final)
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self.sf.write(measure_string)
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def write_control(self, end_time, runlvl=4):
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""" Write the control cards to run and end the simulation """
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# These are guesses...
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if runlvl==1:
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reltol = 0.02 # 2%
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elif runlvl==2:
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reltol = 0.01 # 1%
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elif runlvl==3:
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reltol = 0.005 # 0.5%
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else:
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reltol = 0.001 # 0.1%
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timestep = 10 #ps, was 5ps but ngspice was complaining the timestep was too small in certain tests.
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# UIC is needed for ngspice to converge
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self.sf.write(".TRAN {0}p {1}n UIC\n".format(timestep,end_time))
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self.sf.write(".TEMP {}\n".format(self.temperature))
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if OPTS.spice_name == "ngspice":
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# ngspice sometimes has convergence problems if not using gear method
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# which is more accurate, but slower than the default trapezoid method
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# Do not remove this or it may not converge due to some "pa_00" nodes
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# unless you figure out what these are.
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self.sf.write(".OPTIONS POST=1 RELTOL={0} PROBE method=gear\n".format(reltol))
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else:
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self.sf.write(".OPTIONS POST=1 RUNLVL={0} PROBE\n".format(runlvl))
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# create plots for all signals
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self.sf.write("* probe is used for hspice/xa, while plot is used in ngspice\n")
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if OPTS.debug_level>0:
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if OPTS.spice_name in ["hspice","xa"]:
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self.sf.write(".probe V(*)\n")
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else:
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self.sf.write(".plot V(*)\n")
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else:
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self.sf.write("*.probe V(*)\n")
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self.sf.write("*.plot V(*)\n")
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# end the stimulus file
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self.sf.write(".end\n\n")
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def write_include(self, circuit):
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"""Writes include statements, inputs are lists of model files"""
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includes = self.device_models + [circuit]
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self.sf.write("* {} process corner\n".format(self.process))
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if OPTS.tech_name == "sky130":
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libraries = self.device_libraries
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for item in list(libraries):
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if os.path.isfile(item[0]):
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self.sf.write(".lib \"{0}\" {1}\n".format(item[0], item[1]))
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else:
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debug.error("Could not find spice library: {0}\nSet SPICE_MODEL_DIR to over-ride path.\n".format(item[0]))
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for item in list(includes):
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if os.path.isfile(item):
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self.sf.write(".include \"{0}\"\n".format(item))
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else:
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debug.error("Could not find spice model: {0}\nSet SPICE_MODEL_DIR to over-ride path.\n".format(item))
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def write_supply(self):
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""" Writes supply voltage statements """
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gnd_node_name = "0"
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self.sf.write("V{0} {0} {1} {2}\n".format(self.vdd_name, gnd_node_name, self.voltage))
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#Adding a commented out supply for simulators where gnd and 0 are not global grounds.
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self.sf.write("\n*Nodes gnd and 0 are the same global ground node in ngspice/hspice/xa. Otherwise, this source may be needed.\n")
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self.sf.write("*V{0} {0} {1} {2}\n".format(self.gnd_name, gnd_node_name, 0.0))
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def run_sim(self):
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""" Run hspice in batch mode and output rawfile to parse. """
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temp_stim = "{0}stim.sp".format(OPTS.openram_temp)
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import datetime
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start_time = datetime.datetime.now()
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debug.check(OPTS.spice_exe!="","No spice simulator has been found.")
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if OPTS.spice_name == "xa":
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# Output the xa configurations here. FIXME: Move this to write it once.
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xa_cfg = open("{}xa.cfg".format(OPTS.openram_temp), "w")
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xa_cfg.write("set_sim_level -level 7\n")
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xa_cfg.write("set_powernet_level 7 -node vdd\n")
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xa_cfg.close()
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cmd = "{0} {1} -c {2}xa.cfg -o {2}xa -mt 2".format(OPTS.spice_exe,
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temp_stim,
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OPTS.openram_temp)
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valid_retcode=0
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elif OPTS.spice_name == "hspice":
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# TODO: Should make multithreading parameter a configuration option
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cmd = "{0} -mt 2 -i {1} -o {2}timing".format(OPTS.spice_exe,
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temp_stim,
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OPTS.openram_temp)
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valid_retcode=0
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else:
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# ngspice 27+ supports threading with "set num_threads=4" in the stimulus file or a .spiceinit
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cmd = "{0} -b -o {2}timing.lis {1}".format(OPTS.spice_exe,
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temp_stim,
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OPTS.openram_temp)
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# for some reason, ngspice-25 returns 1 when it only has acceptable warnings
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valid_retcode=1
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spice_stdout = open("{0}spice_stdout.log".format(OPTS.openram_temp), 'w')
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spice_stderr = open("{0}spice_stderr.log".format(OPTS.openram_temp), 'w')
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debug.info(3, cmd)
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retcode = subprocess.call(cmd, stdout=spice_stdout, stderr=spice_stderr, shell=True)
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spice_stdout.close()
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spice_stderr.close()
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if (retcode > valid_retcode):
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debug.error("Spice simulation error: " + cmd, -1)
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else:
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end_time = datetime.datetime.now()
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delta_time = round((end_time-start_time).total_seconds(),1)
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debug.info(2,"*** Spice: {} seconds".format(delta_time))
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