mrg bc8fd4a882 Merge branch 'supply_router' into dev

2021-01-25 11:01:48 -08:00

..

channel_route.py

Update copyright year.

2021-01-22 11:23:28 -08:00

contact.py

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2021-01-22 11:23:28 -08:00

custom_cell_properties.py

Set default port map

2020-11-24 13:27:11 -08:00

custom_layer_properties.py

…

delay_data.py

Update copyright year.

2021-01-22 11:23:28 -08:00

design.py

Merge branch 'supply_router' into dev

2021-01-25 11:01:48 -08:00

errors.py

…

geometry.py

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2021-01-22 11:23:28 -08:00

graph_util.py

Added debug measurements along main delay paths in SRAM. WIP.

2020-11-17 12:43:17 -08:00

hierarchy_design.py

Update copyright year.

2021-01-22 11:23:28 -08:00

hierarchy_layout.py

Merge branch 'supply_router' into dev

2021-01-25 11:01:48 -08:00

hierarchy_spice.py

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2021-01-22 11:23:28 -08:00

lef.py

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2021-01-22 11:23:28 -08:00

pin_layout.py

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2021-01-22 11:23:28 -08:00

power_data.py

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2021-01-22 11:23:28 -08:00

route.py

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utils.py

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vector.py

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verilog.py

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wire_path.py

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wire_spice_model.py

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wire.py

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