Logo
Explore Help
Sign In
luke/OpenRAM
Watch 1
Star 0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
3244e01ca1d516ede1c944040a4c1c9c87682ac8
OpenRAM/compiler/pgates
T
History
Matt Guthaus 3244e01ca1 Add copy power pin function
2018-10-08 09:56:39 -07:00
..
pgate.py
Make bitcell width/height not static. Update modules to use it for pbitcell.
2018-09-04 11:55:22 -07:00
pinv.py
Fixed known typos of the word transition.
2018-09-10 14:27:26 -07:00
pinvbuf.py
Add copy power pin function
2018-10-08 09:56:39 -07:00
pnand2.py
Fixed known typos of the word transition.
2018-09-10 14:27:26 -07:00
pnand3.py
Fixed known typos of the word transition.
2018-09-10 14:27:26 -07:00
pnor2.py
Fixed known typos of the word transition.
2018-09-10 14:27:26 -07:00
precharge.py
Move place function to instance class rather than hierarchy.
2018-08-27 17:25:39 -07:00
ptx.py
Converted all modules to not run create_layout when netlist_only
2018-08-27 16:42:48 -07:00
single_level_column_mux.py
Bank level layout now works with pbitcell and 1RW. Column mux and array have been altered to accomodate multiport. Multiport changes to wordline driver were removed because they were unnecessary.
2018-09-09 22:06:29 -07:00
Powered by Gitea Version: 1.27.2 Page: 2864ms Template: 2ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API