mirror of https://github.com/VLSIDA/OpenRAM.git
74 lines
1.3 KiB
Verilog
74 lines
1.3 KiB
Verilog
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module multibank # (
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DATA_WIDTH = 32,
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ADDR_WIDTH= 8,
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NUM_BANKS=2
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)(
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#<RW_PORTS
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clk,
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addr,
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din,
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csb,
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web,
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dout
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#>RW_PORTS
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#<R_PORTS
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clk,
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addr,
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csb,
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web,
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dout
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#>R_PORTS
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);
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parameter RAM_DEPTH = 1 << ADDR_WIDTH;
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parameter BANK_SEL = (NUM_BANKS <= 2)? 1 :
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(NUM_BANKS <= 4)? 2 :
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(NUM_BANKS <= 8)? 3 :
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(NUM_BANKS <= 16)? 4 : 5;
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input clk;
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input [ADDR_WIDTH -1 : 0] addr;
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input [DATA_WIDTH - 1: 0] din;
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input csb;
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input web;
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output reg [DATA_WIDTH - 1 : 0] dout;
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#!PORT_NUM!0#
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#<BANK_DEFS
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reg csb#$PORT_NUM$#;
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reg web#$PORT_NUM$#;
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reg [DATA_WIDTH - 1 : 0] dout#$PORT_NUM$#;
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#!PORT_NUM!PORT_NUM+1#
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#>BANK_DEFS
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#!PORT_NUM!0#
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#<BANK_INIT
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bank #(DATA_WIDTH, ADDR_WIDTH) bank#$PORT_NUM$# (
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#<BANK_RW_PORTS
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.clk(clk),
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.addr(addr[ADDR_WIDTH - BANK_SEL - 1 : 0]),
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.din(din),
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.csb(csb#$PORT_NUM$#),
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.web(web#$PORT_NUM$#),
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.dout(dout#$PORT_NUM$#)
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#!PORT_NUM!PORT_NUM+1#
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#>BANK_RW_PORTS
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);
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#>BANK_INIT
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always @(posedge clk) begin
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case (addr[ADDR_WIDTH - 1 : ADDR_WIDTH - BANK_SEL])
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#!PORT_NUM!0#
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#<BANK_CASE
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#$PORT_NUM$#: begin
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dout <= dout#$PORT_NUM$#;
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web#$PORT_NUM$# <= web;
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end
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#!PORT_NUM!PORT_NUM+1#
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#>BANK_CASE
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endcase
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end
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endmodule
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