mirror of https://github.com/VLSIDA/OpenRAM.git
451 lines
25 KiB
Python
451 lines
25 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from openram import debug
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from openram import tech
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from openram import OPTS
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from .stimuli import *
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from .trim_spice import *
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from .charutils import *
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from .delay import delay
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from .measurements import *
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class model_check(delay):
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"""Functions to test for the worst case delay in a target SRAM
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The current worst case determines a feasible period for the SRAM then tests
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several bits and record the delay and differences between the bits.
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"""
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def __init__(self, sram, spfile, corner, custom_delaychain=False):
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super().__init__(sram, spfile, corner)
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self.period = tech.spice["feasible_period"]
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self.create_data_names()
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self.custom_delaychain=custom_delaychain
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def create_data_names(self):
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self.wl_meas_name, self.wl_model_name = "wl_measures", "wl_model"
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self.sae_meas_name, self.sae_model_name = "sae_measures", "sae_model"
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self.wl_slew_name, self.sae_slew_name = "wl_slews", "sae_slews"
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self.bl_meas_name, self.bl_slew_name = "bl_measures", "bl_slews"
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self.power_name = "total_power"
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def create_measurement_names(self, port):
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"""
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Create measurement names. The names themselves currently define the type of measurement
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"""
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wl_en_driver_delay_names = ["delay_wl_en_dvr_{0}".format(stage) for stage in range(1, self.get_num_wl_en_driver_stages())]
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wl_driver_delay_names = ["delay_wl_dvr_{0}".format(stage) for stage in range(1, self.get_num_wl_driver_stages())]
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sen_driver_delay_names = ["delay_sen_dvr_{0}".format(stage) for stage in range(1, self.get_num_sen_driver_stages())]
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if self.custom_delaychain:
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dc_delay_names = ["delay_dc_out_final"]
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else:
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dc_delay_names = ["delay_delay_chain_stage_{0}".format(stage) for stage in range(1, self.get_num_delay_stages() + 1)]
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self.wl_delay_meas_names = wl_en_driver_delay_names + ["delay_wl_en", "delay_wl_bar"] + wl_driver_delay_names + ["delay_wl"]
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if port not in self.sram.readonly_ports:
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self.rbl_delay_meas_names = ["delay_gated_clk_nand", "delay_delay_chain_in"] + dc_delay_names
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else:
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self.rbl_delay_meas_names = ["delay_gated_clk_nand"] + dc_delay_names
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self.sae_delay_meas_names = ["delay_pre_sen"] + sen_driver_delay_names + ["delay_sen"]
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# if self.custom_delaychain:
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# self.delay_chain_indices = (len(self.rbl_delay_meas_names), len(self.rbl_delay_meas_names)+1)
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# else:
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self.delay_chain_indices = (len(self.rbl_delay_meas_names) - len(dc_delay_names), len(self.rbl_delay_meas_names))
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# Create slew measurement names
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wl_en_driver_slew_names = ["slew_wl_en_dvr_{0}".format(stage) for stage in range(1, self.get_num_wl_en_driver_stages())]
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wl_driver_slew_names = ["slew_wl_dvr_{0}".format(stage) for stage in range(1, self.get_num_wl_driver_stages())]
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sen_driver_slew_names = ["slew_sen_dvr_{0}".format(stage) for stage in range(1, self.get_num_sen_driver_stages())]
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if self.custom_delaychain:
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dc_slew_names = ["slew_dc_out_final"]
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else:
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dc_slew_names = ["slew_delay_chain_stage_{0}".format(stage) for stage in range(1, self.get_num_delay_stages() + 1)]
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self.wl_slew_meas_names = ["slew_wl_gated_clk_bar"] + wl_en_driver_slew_names + ["slew_wl_en", "slew_wl_bar"] + wl_driver_slew_names + ["slew_wl"]
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if port not in self.sram.readonly_ports:
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self.rbl_slew_meas_names = ["slew_rbl_gated_clk_bar", "slew_gated_clk_nand", "slew_delay_chain_in"] + dc_slew_names
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else:
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self.rbl_slew_meas_names = ["slew_rbl_gated_clk_bar"] + dc_slew_names
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self.sae_slew_meas_names = ["slew_replica_bl0", "slew_pre_sen"] + sen_driver_slew_names + ["slew_sen"]
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self.bitline_meas_names = ["delay_wl_to_bl", "delay_bl_to_dout"]
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self.power_meas_names = ["read0_power"]
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def create_signal_names(self, port):
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"""Creates list of the signal names used in the spice file along the wl and sen paths.
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Names are re-harded coded here; i.e. the names are hardcoded in most of OpenRAM and are
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replicated here.
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"""
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delay.create_signal_names(self)
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# Signal names are all hardcoded, need to update to make it work for probe address and different configurations.
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wl_en_driver_signals = ["Xsram{1}Xcontrol{{}}.Xbuf_wl_en.Zb{0}_int".format(stage, OPTS.hier_seperator) for stage in range(1, self.get_num_wl_en_driver_stages())]
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wl_driver_signals = ["Xsram{2}Xbank0{2}Xwordline_driver{{}}{2}Xwl_driver_inv{0}{2}Zb{1}_int".format(self.wordline_row, stage, OPTS.hier_seperator) for stage in range(1, self.get_num_wl_driver_stages())]
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sen_driver_signals = ["Xsram{1}Xcontrol{{}}{1}Xbuf_s_en{1}Zb{0}_int".format(stage, OPTS.hier_seperator) for stage in range(1, self.get_num_sen_driver_stages())]
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if self.custom_delaychain:
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delay_chain_signal_names = []
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else:
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delay_chain_signal_names = ["Xsram{1}Xcontrol{{}}{1}Xreplica_bitline{1}Xdelay_chain{1}dout_{0}".format(stage, OPTS.hier_seperator) for stage in range(1, self.get_num_delay_stages())]
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if len(self.sram.all_ports) > 1:
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port_format = '{}'
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else:
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port_format = ''
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self.wl_signal_names = ["Xsram{0}Xcontrol{{}}{0}gated_clk_bar".format(OPTS.hier_seperator)] + \
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wl_en_driver_signals + \
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["Xsram{0}wl_en{{}}".format(OPTS.hier_seperator),
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"Xsram{1}Xbank0{1}Xwordline_driver{{}}{1}wl_bar_{0}".format(self.wordline_row,
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OPTS.hier_seperator)] + \
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wl_driver_signals + \
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["Xsram{2}Xbank0{2}wl{0}_{1}".format(port_format,
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self.wordline_row,
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OPTS.hier_seperator)]
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pre_delay_chain_names = ["Xsram.Xcontrol{{}}{0}gated_clk_bar".format(OPTS.hier_seperator)]
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if port not in self.sram.readonly_ports:
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pre_delay_chain_names+= ["Xsram{0}Xcontrol{{}}{0}Xand2_rbl_in{0}zb_int".format(OPTS.hier_seperator),
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"Xsram{0}Xcontrol{{}}{0}rbl_in".format(OPTS.hier_seperator)]
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self.rbl_en_signal_names = pre_delay_chain_names + \
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delay_chain_signal_names + \
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["Xsram{0}Xcontrol{{}}{0}Xreplica_bitline{0}delayed_en".format(OPTS.hier_seperator)]
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self.sae_signal_names = ["Xsram{0}Xcontrol{{}}{0}Xreplica_bitline{0}bl0_0".format(OPTS.hier_seperator),
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"Xsram{0}Xcontrol{{}}{0}pre_s_en".format(OPTS.hier_seperator)] + \
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sen_driver_signals + \
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["Xsram{0}s_en{{}}".format(OPTS.hier_seperator)]
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self.bl_signal_names = ["Xsram{2}Xbank0{2}wl{0}_{1}".format(port_format, self.wordline_row, OPTS.hier_seperator),
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"Xsram{2}Xbank0{2}bl{0}_{1}".format(port_format, self.bitline_column, OPTS.hier_seperator),
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"{0}{{}}_{1}".format(self.dout_name, self.probe_data)] # Empty values are the port and probe data bit
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def create_measurement_objects(self):
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"""Create the measurements used for read and write ports"""
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self.create_wordline_meas_objs()
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self.create_sae_meas_objs()
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self.create_bl_meas_objs()
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self.create_power_meas_objs()
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self.all_measures = self.wl_meas_objs + self.sae_meas_objs + self.bl_meas_objs + self.power_meas_objs
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def create_power_meas_objs(self):
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"""Create power measurement object. Only one."""
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self.power_meas_objs = []
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self.power_meas_objs.append(power_measure(self.power_meas_names[0], "FALL", measure_scale=1e3))
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def create_wordline_meas_objs(self):
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"""Create the measurements to measure the wordline path from the gated_clk_bar signal"""
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self.wl_meas_objs = []
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trig_dir = "RISE"
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targ_dir = "FALL"
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for i in range(1, len(self.wl_signal_names)):
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self.wl_meas_objs.append(delay_measure(self.wl_delay_meas_names[i - 1],
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self.wl_signal_names[i - 1],
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self.wl_signal_names[i],
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trig_dir,
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targ_dir,
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measure_scale=1e9))
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self.wl_meas_objs.append(slew_measure(self.wl_slew_meas_names[i - 1],
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self.wl_signal_names[i - 1],
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trig_dir,
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measure_scale=1e9))
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temp_dir = trig_dir
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trig_dir = targ_dir
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targ_dir = temp_dir
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self.wl_meas_objs.append(slew_measure(self.wl_slew_meas_names[-1], self.wl_signal_names[-1], trig_dir, measure_scale=1e9))
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def create_bl_meas_objs(self):
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"""Create the measurements to measure the bitline to dout, static stages"""
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# Bitline has slightly different measurements, objects appends hardcoded.
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self.bl_meas_objs = []
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trig_dir, targ_dir = "RISE", "FALL" # Only check read 0
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self.bl_meas_objs.append(delay_measure(self.bitline_meas_names[0],
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self.bl_signal_names[0],
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self.bl_signal_names[-1],
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trig_dir,
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targ_dir,
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measure_scale=1e9))
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def create_sae_meas_objs(self):
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"""Create the measurements to measure the sense amp enable path from the gated_clk_bar signal. The RBL splits this path into two."""
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self.sae_meas_objs = []
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trig_dir = "RISE"
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targ_dir = "FALL"
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# Add measurements from gated_clk_bar to RBL
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for i in range(1, len(self.rbl_en_signal_names)):
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self.sae_meas_objs.append(delay_measure(self.rbl_delay_meas_names[i - 1],
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self.rbl_en_signal_names[i - 1],
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self.rbl_en_signal_names[i],
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trig_dir,
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targ_dir,
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measure_scale=1e9))
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self.sae_meas_objs.append(slew_measure(self.rbl_slew_meas_names[i - 1],
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self.rbl_en_signal_names[i - 1],
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trig_dir,
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measure_scale=1e9))
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temp_dir = trig_dir
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trig_dir = targ_dir
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targ_dir = temp_dir
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if self.custom_delaychain: # Hack for custom delay chains
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self.sae_meas_objs[-2] = delay_measure(self.rbl_delay_meas_names[-1],
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self.rbl_en_signal_names[-2],
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self.rbl_en_signal_names[-1],
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"RISE",
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"RISE",
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measure_scale=1e9)
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self.sae_meas_objs.append(slew_measure(self.rbl_slew_meas_names[-1],
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self.rbl_en_signal_names[-1],
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trig_dir,
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measure_scale=1e9))
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# Add measurements from rbl_out to sae. Trigger directions do not invert from previous stage due to RBL.
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trig_dir = "FALL"
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targ_dir = "RISE"
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for i in range(1, len(self.sae_signal_names)):
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self.sae_meas_objs.append(delay_measure(self.sae_delay_meas_names[i - 1],
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self.sae_signal_names[i - 1],
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self.sae_signal_names[i],
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trig_dir,
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targ_dir,
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measure_scale=1e9))
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self.sae_meas_objs.append(slew_measure(self.sae_slew_meas_names[i - 1],
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self.sae_signal_names[i - 1],
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trig_dir,
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measure_scale=1e9))
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temp_dir = trig_dir
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trig_dir = targ_dir
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targ_dir = temp_dir
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self.sae_meas_objs.append(slew_measure(self.sae_slew_meas_names[-1],
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self.sae_signal_names[-1],
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trig_dir,
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measure_scale=1e9))
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def write_delay_measures(self):
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"""
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Write the measure statements to quantify the delay and power results for all targeted ports.
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"""
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self.sf.write("\n* Measure statements for delay and power\n")
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# Output some comments to aid where cycles start and what is happening
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for comment in self.cycle_comments:
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self.sf.write("* {}\n".format(comment))
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for read_port in self.targ_read_ports:
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self.write_measures_read_port(read_port)
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def get_delay_measure_variants(self, port, measure_obj):
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"""Get the measurement values that can either vary from simulation to simulation (vdd, address)
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or port to port (time delays)"""
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# Return value is intended to match the delay measure format: trig_td, targ_td, vdd, port
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# Assuming only read 0 for now
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debug.info(3, "Power measurement={}".format(measure_obj))
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if (type(measure_obj) is delay_measure or type(measure_obj) is slew_measure):
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meas_cycle_delay = self.cycle_times[self.measure_cycles[port]["read0"]] + self.period / 2
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return (meas_cycle_delay, meas_cycle_delay, self.vdd_voltage, port)
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elif type(measure_obj) is power_measure:
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return self.get_power_measure_variants(port, measure_obj, "read")
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else:
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debug.error("Measurement not recognized by the model checker.",1)
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def get_power_measure_variants(self, port, power_obj, operation):
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"""Get the measurement values that can either vary port to port (time delays)"""
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# Return value is intended to match the power measure format: t_initial, t_final, port
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t_initial = self.cycle_times[self.measure_cycles[port]["read0"]]
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t_final = self.cycle_times[self.measure_cycles[port]["read0"] + 1]
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return (t_initial, t_final, port)
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def write_measures_read_port(self, port):
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"""
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Write the measure statements for all nodes along the wordline path.
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"""
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# add measure statements for delays/slews
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for measure in self.all_measures:
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measure_variant_inp_tuple = self.get_delay_measure_variants(port, measure)
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measure.write_measure(self.stim, measure_variant_inp_tuple)
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def get_measurement_values(self, meas_objs, port):
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"""Gets the delays and slews from a specified port from the spice output file and returns them as lists."""
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delay_meas_list = []
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slew_meas_list = []
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power_meas_list=[]
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for measure in meas_objs:
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measure_value = measure.retrieve_measure(port=port)
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if type(measure_value) != float:
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debug.error("Failed to Measure Value:\n\t\t{}={}".format(measure.name, measure_value),1)
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if type(measure) is delay_measure:
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delay_meas_list.append(measure_value)
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elif type(measure)is slew_measure:
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slew_meas_list.append(measure_value)
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elif type(measure)is power_measure:
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power_meas_list.append(measure_value)
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else:
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debug.error("Measurement object not recognized.", 1)
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return delay_meas_list, slew_meas_list, power_meas_list
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def run_delay_simulation(self):
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"""
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This tries to simulate a period and checks if the result works. If
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so, it returns True and the delays, slews, and powers. It
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works on the trimmed netlist by default, so powers do not
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include leakage of all cells.
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"""
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# Sanity Check
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debug.check(self.period > 0, "Target simulation period non-positive")
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wl_delay_result = [[] for i in self.all_ports]
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wl_slew_result = [[] for i in self.all_ports]
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sae_delay_result = [[] for i in self.all_ports]
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sae_slew_result = [[] for i in self.all_ports]
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bl_delay_result = [[] for i in self.all_ports]
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bl_slew_result = [[] for i in self.all_ports]
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power_result = [[] for i in self.all_ports]
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# Checking from not data_value to data_value
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self.write_delay_stimulus()
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self.stim.run_sim() # running sim prodoces spice output file.
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# Retrieve the results from the output file
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for port in self.targ_read_ports:
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# Parse and check the voltage measurements
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wl_delay_result[port], wl_slew_result[port], _ = self.get_measurement_values(self.wl_meas_objs, port)
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sae_delay_result[port], sae_slew_result[port], _ = self.get_measurement_values(self.sae_meas_objs, port)
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bl_delay_result[port], bl_slew_result[port], _ = self.get_measurement_values(self.bl_meas_objs, port)
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_, __, power_result[port] = self.get_measurement_values(self.power_meas_objs, port)
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return (True, wl_delay_result, sae_delay_result, wl_slew_result, sae_slew_result, bl_delay_result, bl_slew_result, power_result)
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def get_model_delays(self, port):
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"""Get model delays based on port. Currently assumes single RW port."""
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return self.sram.control_logic_rw.get_wl_sen_delays()
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def get_num_delay_stages(self):
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"""Gets the number of stages in the delay chain from the control logic"""
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return len(self.sram.control_logic_rw.replica_bitline.delay_fanout_list)
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def get_num_delay_fanout_list(self):
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"""Gets the number of stages in the delay chain from the control logic"""
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return self.sram.control_logic_rw.replica_bitline.delay_fanout_list
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def get_num_delay_stage_fanout(self):
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"""Gets fanout in each stage in the delay chain. Assumes each stage is the same"""
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return self.sram.control_logic_rw.replica_bitline.delay_fanout_list[0]
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def get_num_wl_en_driver_stages(self):
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"""Gets the number of stages in the wl_en driver from the control logic"""
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return self.sram.control_logic_rw.wl_en_driver.num_stages
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def get_num_sen_driver_stages(self):
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"""Gets the number of stages in the sen driver from the control logic"""
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return self.sram.control_logic_rw.s_en_driver.num_stages
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def get_num_wl_driver_stages(self):
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"""Gets the number of stages in the wordline driver from the control logic"""
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return self.sram.bank.wordline_driver.inv.num_stages
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def scale_delays(self, delay_list):
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"""Takes in a list of measured delays and convert it to simple units to easily compare to model values."""
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converted_values = []
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# Calculate average
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total = 0
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for meas_value in delay_list:
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total+=meas_value
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average = total / len(delay_list)
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# Convert values
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for meas_value in delay_list:
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converted_values.append(meas_value / average)
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return converted_values
|
|
|
|
def min_max_normalization(self, value_list):
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"""Re-scales input values on a range from 0-1 where min(list)=0, max(list)=1"""
|
|
scaled_values = []
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min_max_diff = max(value_list) - min(value_list)
|
|
average = sum(value_list) / len(value_list)
|
|
for value in value_list:
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scaled_values.append((value - average) / (min_max_diff))
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return scaled_values
|
|
|
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def calculate_error_l2_norm(self, list_a, list_b):
|
|
"""Calculates error between two lists using the l2 norm"""
|
|
error_list = []
|
|
for val_a, val_b in zip(list_a, list_b):
|
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error_list.append((val_a - val_b)**2)
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|
return error_list
|
|
|
|
def compare_measured_and_model(self, measured_vals, model_vals):
|
|
"""First scales both inputs into similar ranges and then compares the error between both."""
|
|
scaled_meas = self.min_max_normalization(measured_vals)
|
|
debug.info(1, "Scaled measurements:\n{0}".format(scaled_meas))
|
|
scaled_model = self.min_max_normalization(model_vals)
|
|
debug.info(1, "Scaled model:\n{0}".format(scaled_model))
|
|
errors = self.calculate_error_l2_norm(scaled_meas, scaled_model)
|
|
debug.info(1, "Errors:\n{0}\n".format(errors))
|
|
|
|
def analyze(self, probe_address, probe_data, slews, loads, port):
|
|
"""Measures entire delay path along the wordline and sense amp enable and compare it to the model delays."""
|
|
self.load=max(loads)
|
|
self.slew=max(slews)
|
|
self.set_probe(probe_address, probe_data)
|
|
self.create_signal_names(port)
|
|
self.create_measurement_names(port)
|
|
self.create_measurement_objects()
|
|
data_dict = {}
|
|
|
|
read_port = self.read_ports[0] # only test the first read port
|
|
read_port = port
|
|
self.targ_read_ports = [read_port]
|
|
self.targ_write_ports = [self.write_ports[0]]
|
|
debug.info(1, "Model test: corner {0}".format(self.corner))
|
|
(success, wl_delays, sae_delays, wl_slews, sae_slews, bl_delays, bl_slews, powers)=self.run_delay_simulation()
|
|
debug.check(success, "Model measurements Failed: period={0}".format(self.period))
|
|
|
|
debug.info(1, "Measured Wordline delays (ns):\n\t {0}".format(wl_delays[read_port]))
|
|
debug.info(1, "Measured Wordline slews:\n\t {0}".format(wl_slews[read_port]))
|
|
debug.info(1, "Measured SAE delays (ns):\n\t {0}".format(sae_delays[read_port]))
|
|
debug.info(1, "Measured SAE slews:\n\t {0}".format(sae_slews[read_port]))
|
|
debug.info(1, "Measured Bitline delays (ns):\n\t {0}".format(bl_delays[read_port]))
|
|
|
|
data_dict[self.wl_meas_name] = wl_delays[read_port]
|
|
data_dict[self.sae_meas_name] = sae_delays[read_port]
|
|
data_dict[self.wl_slew_name] = wl_slews[read_port]
|
|
data_dict[self.sae_slew_name] = sae_slews[read_port]
|
|
data_dict[self.bl_meas_name] = bl_delays[read_port]
|
|
data_dict[self.power_name] = powers[read_port]
|
|
|
|
if OPTS.auto_delay_chain_sizing: # Model is not used in this case
|
|
wl_model_delays, sae_model_delays = self.get_model_delays(read_port)
|
|
debug.info(1, "Wordline model delays:\n\t {0}".format(wl_model_delays))
|
|
debug.info(1, "SAE model delays:\n\t {0}".format(sae_model_delays))
|
|
data_dict[self.wl_model_name] = wl_model_delays
|
|
data_dict[self.sae_model_name] = sae_model_delays
|
|
|
|
# Some evaluations of the model and measured values
|
|
# debug.info(1, "Comparing wordline measurements and model.")
|
|
# self.compare_measured_and_model(wl_delays[read_port], wl_model_delays)
|
|
# debug.info(1, "Comparing SAE measurements and model")
|
|
# self.compare_measured_and_model(sae_delays[read_port], sae_model_delays)
|
|
|
|
return data_dict
|
|
|
|
def get_all_signal_names(self):
|
|
"""Returns all signals names as a dict indexed by hardcoded names. Useful for writing the head of the CSV."""
|
|
name_dict = {}
|
|
# Signal names are more descriptive than the measurement names, first value trimmed to match size of measurements names.
|
|
name_dict[self.wl_meas_name] = self.wl_signal_names[1:]
|
|
name_dict[self.sae_meas_name] = self.rbl_en_signal_names[1:] + self.sae_signal_names[1:]
|
|
name_dict[self.wl_slew_name] = self.wl_slew_meas_names
|
|
name_dict[self.sae_slew_name] = self.rbl_slew_meas_names + self.sae_slew_meas_names
|
|
name_dict[self.bl_meas_name] = self.bitline_meas_names[0:1]
|
|
name_dict[self.power_name] = self.power_meas_names
|
|
# pname_dict[self.wl_slew_name] = self.wl_slew_meas_names
|
|
|
|
if OPTS.auto_delay_chain_sizing:
|
|
name_dict[self.wl_model_name] = name_dict["wl_measures"] # model uses same names as measured.
|
|
name_dict[self.sae_model_name] = name_dict["sae_measures"]
|
|
|
|
return name_dict
|