mirror of https://github.com/VLSIDA/OpenRAM.git
45 lines
1.8 KiB
Python
45 lines
1.8 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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class wire_spice_model():
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"""
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This is the spice class to represent a wire
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"""
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def __init__(self, lump_num, wire_length, wire_width):
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self.lump_num = lump_num # the number of segment the wire delay has
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self.wire_c = self.cal_wire_c(wire_length, wire_width) # c in each segment
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self.wire_r = self.cal_wire_r(wire_length, wire_width) # r in each segment
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def cal_wire_c(self, wire_length, wire_width):
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from openram.tech import spice
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# Convert the F/um^2 to fF/um^2 then multiple by width and length
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# FIXME: shouldn't it be 1e15?
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total_c = (spice["wire_unit_c"]*1e12) * wire_length * wire_width
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wire_c = total_c / self.lump_num
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return wire_c
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def cal_wire_r(self, wire_length, wire_width):
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from openram.tech import spice
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total_r = spice["wire_unit_r"] * wire_length / wire_width
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wire_r = total_r / self.lump_num
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return wire_r
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def return_input_cap(self):
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return 0.5 * self.wire_c * self.lump_num
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def return_delay_over_wire(self, slew, swing = 0.5):
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# delay will be sum of arithmetic sequence start from
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# rc to self.lump_num*rc with step of rc
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swing_factor = abs(math.log(1-swing)) # time constant based on swing
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sum_factor = (1+self.lump_num) * self.lump_num * 0.5 # sum of the arithmetic sequence
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delay = sum_factor * swing_factor * self.wire_r * self.wire_c
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slew = delay * 2 + slew
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result= delay_data(delay, slew)
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return result
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