mirror of https://github.com/VLSIDA/OpenRAM.git
595 lines
30 KiB
Python
595 lines
30 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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from vector import vector
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from sram_base import sram_base
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from contact import m2_via
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from globals import OPTS
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class sram_1bank(sram_base):
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"""
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Procedures specific to a one bank SRAM.
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"""
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def __init__(self, name, sram_config):
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sram_base.__init__(self, name, sram_config)
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def create_modules(self):
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"""
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This adds the modules for a single bank SRAM with control
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logic.
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"""
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self.bank_inst=self.create_bank(0)
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self.control_logic_insts = self.create_control_logic()
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self.row_addr_dff_insts = self.create_row_addr_dff()
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if self.col_addr_dff:
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self.col_addr_dff_insts = self.create_col_addr_dff()
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if self.write_size:
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self.wmask_dff_insts = self.create_wmask_dff()
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self.data_dff_insts = self.create_data_dff()
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else:
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self.data_dff_insts = self.create_data_dff()
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if self.num_spare_cols:
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self.spare_wen_dff_insts = self.create_spare_wen_dff()
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else:
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self.num_spare_cols = 0
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def place_instances(self):
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"""
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This places the instances for a single bank SRAM with control
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logic and up to 2 ports.
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"""
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# No orientation or offset
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self.place_bank(self.bank_inst, [0, 0], 1, 1)
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# The control logic is placed such that the vertical center (between the delay/RBL and
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# the actual control logic is aligned with the vertical center of the bank (between
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# the sense amps/column mux and cell array)
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# The x-coordinate is placed to allow a single clock wire (plus an extra pitch)
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# up to the row address DFFs.
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control_pos = [None] * len(self.all_ports)
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row_addr_pos = [None] * len(self.all_ports)
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col_addr_pos = [None] * len(self.all_ports)
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wmask_pos = [None] * len(self.all_ports)
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spare_wen_pos = [None] * len(self.all_ports)
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data_pos = [None] * len(self.all_ports)
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# These positions utilize the channel route sizes.
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# FIXME: Auto-compute these rather than manual computation.
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# If a horizontal channel, they rely on the vertical channel non-preferred (contacted) pitch.
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# If a vertical channel, they rely on the horizontal channel non-preferred (contacted) pitch.
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# So, m3 non-pref pitch means that this is routed on the m2 layer.
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self.data_bus_gap = self.m4_nonpref_pitch * 2
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# Spare wen are on a separate layer so not included
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# Start with 1 track minimum
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self.data_bus_size = [1] * len(self.all_ports)
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for port in self.all_ports:
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# All ports need the col addr flops
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self.data_bus_size[port] += self.col_addr_size
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# Write ports need the data input flops and write mask flops
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if port in self.write_ports:
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self.data_bus_size[port] += self.num_wmasks + self.word_size
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# This is for the din pins that get routed in the same channel
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# when we have dout and din together
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if port in self.readwrite_ports:
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self.data_bus_size[port] += self.word_size
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# Convert to length
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self.data_bus_size[port] *= self.m4_nonpref_pitch
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# Add the gap in unit length
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self.data_bus_size[port] += self.data_bus_gap
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# Port 0
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port = 0
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# This includes 2 M2 pitches for the row addr clock line.
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# The delay line is aligned with the bitcell array while the control logic is aligned with the port_data
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# using the control_logic_center value.
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control_pos[port] = vector(-self.control_logic_insts[port].width - 2 * self.m2_pitch,
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self.bank.bank_array_ll.y - self.control_logic_insts[port].mod.control_logic_center.y)
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self.control_logic_insts[port].place(control_pos[port])
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# The row address bits are placed above the control logic aligned on the right.
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x_offset = self.control_logic_insts[port].rx() - self.row_addr_dff_insts[port].width
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# It is above the control logic but below the top of the bitcell array
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y_offset = max(self.control_logic_insts[port].uy(), self.bank_inst.uy() - self.row_addr_dff_insts[port].height)
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row_addr_pos[port] = vector(x_offset, y_offset)
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self.row_addr_dff_insts[port].place(row_addr_pos[port])
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# Add the col address flops below the bank to the right of the control logic
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x_offset = self.control_logic_insts[port].rx() + self.dff.width
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y_offset = - self.data_bus_size[port] - self.dff.height
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if self.col_addr_dff:
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col_addr_pos[port] = vector(x_offset,
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y_offset)
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self.col_addr_dff_insts[port].place(col_addr_pos[port])
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x_offset = self.col_addr_dff_insts[port].rx()
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else:
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col_addr_pos[port] = vector(x_offset, 0)
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if port in self.write_ports:
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if self.write_size:
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# Add the write mask flops below the write mask AND array.
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wmask_pos[port] = vector(x_offset,
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y_offset)
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self.wmask_dff_insts[port].place(wmask_pos[port])
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x_offset = self.wmask_dff_insts[port].rx()
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# Add the data flops below the write mask flops.
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data_pos[port] = vector(x_offset,
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y_offset)
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self.data_dff_insts[port].place(data_pos[port])
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x_offset = self.data_dff_insts[port].rx()
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# Add spare write enable flops to the right of data flops since the spare columns
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# will be on the right
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if self.num_spare_cols:
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spare_wen_pos[port] = vector(x_offset,
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y_offset)
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self.spare_wen_dff_insts[port].place(spare_wen_pos[port])
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x_offset = self.spare_wen_dff_insts[port].rx()
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else:
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wmask_pos[port] = vector(x_offset, y_offset)
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data_pos[port] = vector(x_offset, y_offset)
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spare_wen_pos[port] = vector(x_offset, y_offset)
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if len(self.all_ports)>1:
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# Port 1
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port = 1
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# This includes 2 M2 pitches for the row addr clock line
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# The delay line is aligned with the bitcell array while the control logic is aligned with the port_data
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# using the control_logic_center value.
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control_pos[port] = vector(self.bank_inst.rx() + self.control_logic_insts[port].width + 2 * self.m2_pitch,
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self.bank.bank_array_ur.y
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+ self.control_logic_insts[port].height
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- self.control_logic_insts[port].height
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+ self.control_logic_insts[port].mod.control_logic_center.y)
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self.control_logic_insts[port].place(control_pos[port], mirror="XY")
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# The row address bits are placed above the control logic aligned on the left.
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x_offset = control_pos[port].x - self.control_logic_insts[port].width + self.row_addr_dff_insts[port].width
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# It is below the control logic but below the bottom of the bitcell array
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y_offset = min(self.control_logic_insts[port].by(), self.bank_inst.by() + self.row_addr_dff_insts[port].height)
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row_addr_pos[port] = vector(x_offset, y_offset)
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self.row_addr_dff_insts[port].place(row_addr_pos[port], mirror="XY")
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# Add the col address flops below the bank to the right of the control logic
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x_offset = self.control_logic_insts[port].lx() - 2 * self.dff.width
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y_offset = self.bank.height + self.data_bus_size[port] + self.dff.height
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if self.col_addr_dff:
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col_addr_pos[port] = vector(x_offset,
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y_offset)
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self.col_addr_dff_insts[port].place(col_addr_pos[port], mirror="XY")
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x_offset = self.col_addr_dff_insts[port].lx() - self.col_addr_dff_insts[port].width
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else:
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col_addr_pos[port] = vector(x_offset, y_offset)
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if port in self.write_ports:
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# Add spare write enable flops to the right of the data flops since the spare
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# columns will be on the left
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if self.num_spare_cols:
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spare_wen_pos[port] = vector(x_offset - self.spare_wen_dff_insts[port].width,
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y_offset)
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self.spare_wen_dff_insts[port].place(spare_wen_pos[port], mirror="MX")
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x_offset = self.spare_wen_dff_insts[port].lx()
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if self.write_size:
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# Add the write mask flops below the write mask AND array.
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wmask_pos[port] = vector(x_offset - self.wmask_dff_insts[port].width,
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y_offset)
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self.wmask_dff_insts[port].place(wmask_pos[port], mirror="MX")
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x_offset = self.wmask_dff_insts[port].lx()
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# Add the data flops below the write mask flops.
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data_pos[port] = vector(x_offset - self.data_dff_insts[port].width,
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y_offset)
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self.data_dff_insts[port].place(data_pos[port], mirror="MX")
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else:
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wmask_pos[port] = vector(x_offset, y_offset)
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data_pos[port] = vector(x_offset, y_offset)
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spare_wen_pos[port] = vector(x_offset, y_offset)
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def add_layout_pins(self):
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"""
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Add the top-level pins for a single bank SRAM with control.
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"""
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highest_coord = self.find_highest_coords()
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lowest_coord = self.find_lowest_coords()
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bbox = [lowest_coord, highest_coord]
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for port in self.all_ports:
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# Depending on the port, use the bottom/top or left/right sides
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# Port 0 is left/bottom
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# Port 1 is right/top
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bottom_or_top = "bottom" if port==0 else "top"
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left_or_right = "left" if port==0 else "right"
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# Connect the control pins as inputs
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for signal in self.control_logic_inputs[port]:
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if signal == "clk":
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continue
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if OPTS.perimeter_pins:
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self.add_perimeter_pin(name=signal + "{}".format(port),
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pin=self.control_logic_insts[port].get_pin(signal),
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side=left_or_right,
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bbox=bbox)
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else:
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self.copy_layout_pin(self.control_logic_insts[port],
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signal,
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signal + "{}".format(port))
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if OPTS.perimeter_pins:
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self.add_perimeter_pin(name="clk{}".format(port),
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pin=self.control_logic_insts[port].get_pin("clk"),
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side=bottom_or_top,
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bbox=bbox)
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else:
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self.copy_layout_pin(self.control_logic_insts[port],
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"clk",
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"clk{}".format(port))
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# Data input pins go to BOTTOM/TOP
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din_ports = []
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if port in self.write_ports:
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for bit in range(self.word_size + self.num_spare_cols):
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if OPTS.perimeter_pins:
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p = self.add_perimeter_pin(name="din{0}[{1}]".format(port, bit),
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pin=self.data_dff_insts[port].get_pin("din_{0}".format(bit)),
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side=bottom_or_top,
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bbox=bbox)
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din_ports.append(p)
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else:
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self.copy_layout_pin(self.data_dff_insts[port],
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"din_{}".format(bit),
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"din{0}[{1}]".format(port, bit))
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# Data output pins go to BOTTOM/TOP
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if port in self.readwrite_ports and OPTS.perimeter_pins:
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for bit in range(self.word_size + self.num_spare_cols):
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# This should be routed next to the din pin
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p = din_ports[bit]
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self.add_layout_pin_rect_center(text="dout{0}[{1}]".format(port, bit),
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layer=p.layer,
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offset=p.center() + vector(self.m3_pitch, 0),
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width=p.width(),
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height=p.height())
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elif port in self.read_ports:
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for bit in range(self.word_size + self.num_spare_cols):
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if OPTS.perimeter_pins:
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# This should have a clear route to the perimeter if there are no din routes
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self.add_perimeter_pin(name="dout{0}[{1}]".format(port, bit),
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pin=self.bank_inst.get_pin("dout{0}_{1}".format(port, bit)),
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side=bottom_or_top,
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bbox=bbox)
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else:
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self.copy_layout_pin(self.bank_inst,
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"dout{0}_{1}".format(port, bit),
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"dout{0}[{1}]".format(port, bit))
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# Lower address bits go to BOTTOM/TOP
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for bit in range(self.col_addr_size):
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if OPTS.perimeter_pins:
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self.add_perimeter_pin(name="addr{0}[{1}]".format(port, bit),
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pin=self.col_addr_dff_insts[port].get_pin("din_{}".format(bit)),
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side=bottom_or_top,
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bbox=bbox)
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else:
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self.copy_layout_pin(self.col_addr_dff_insts[port],
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"din_{}".format(bit),
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"addr{0}[{1}]".format(port, bit))
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# Upper address bits go to LEFT/RIGHT
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for bit in range(self.row_addr_size):
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if OPTS.perimeter_pins:
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self.add_perimeter_pin(name="addr{0}[{1}]".format(port, bit + self.col_addr_size),
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pin=self.row_addr_dff_insts[port].get_pin("din_{}".format(bit)),
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side=left_or_right,
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bbox=bbox)
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else:
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self.copy_layout_pin(self.row_addr_dff_insts[port],
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"din_{}".format(bit),
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"addr{0}[{1}]".format(port, bit + self.col_addr_size))
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# Write mask pins go to BOTTOM/TOP
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if port in self.write_ports:
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if self.write_size:
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for bit in range(self.num_wmasks):
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if OPTS.perimeter_pins:
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self.add_perimeter_pin(name="wmask{0}[{1}]".format(port, bit),
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pin=self.wmask_dff_insts[port].get_pin("din_{}".format(bit)),
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side=bottom_or_top,
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bbox=bbox)
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else:
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self.copy_layout_pin(self.wmask_dff_insts[port],
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"din_{}".format(bit),
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"wmask{0}[{1}]".format(port, bit))
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# Spare wen pins go to BOTTOM/TOP
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if port in self.write_ports:
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for bit in range(self.num_spare_cols):
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if OPTS.perimeter_pins:
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self.add_perimeter_pin(name="spare_wen{0}[{1}]".format(port, bit),
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pin=self.spare_wen_dff_insts[port].get_pin("din_{}".format(bit)),
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side=left_or_right,
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bbox=bbox)
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else:
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self.copy_layout_pin(self.spare_wen_dff_insts[port],
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"din_{}".format(bit),
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"spare_wen{0}[{1}]".format(port, bit))
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def route_layout(self):
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""" Route a single bank SRAM """
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self.add_layout_pins()
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self.route_clk()
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self.route_control_logic()
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self.route_row_addr_dff()
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for port in self.all_ports:
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self.route_dff(port)
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def route_dff(self, port):
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route_map = []
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# column mux dff is routed on it's own since it is to the far end
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# decoder inputs are min pitch M2, so need to use lower layer stack
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if self.col_addr_size > 0:
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dff_names = ["dout_{}".format(x) for x in range(self.col_addr_size)]
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dff_pins = [self.col_addr_dff_insts[port].get_pin(x) for x in dff_names]
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bank_names = ["addr{0}_{1}".format(port, x) for x in range(self.col_addr_size)]
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bank_pins = [self.bank_inst.get_pin(x) for x in bank_names]
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route_map.extend(list(zip(bank_pins, dff_pins)))
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if port == 0:
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offset = vector(self.control_logic_insts[port].rx() + self.dff.width,
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- self.data_bus_size[port] + 2 * self.m1_pitch)
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else:
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offset = vector(0,
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self.bank.height + 2 * self.m1_space)
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self.create_horizontal_channel_route(netlist=route_map,
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offset=offset,
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layer_stack=self.m1_stack)
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route_map = []
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# wmask dff
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if self.num_wmasks > 0 and port in self.write_ports:
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dff_names = ["dout_{}".format(x) for x in range(self.num_wmasks)]
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dff_pins = [self.wmask_dff_insts[port].get_pin(x) for x in dff_names]
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bank_names = ["bank_wmask{0}_{1}".format(port, x) for x in range(self.num_wmasks)]
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bank_pins = [self.bank_inst.get_pin(x) for x in bank_names]
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route_map.extend(list(zip(bank_pins, dff_pins)))
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if port in self.write_ports:
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# synchronized inputs from data dff
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dff_names = ["dout_{}".format(x) for x in range(self.word_size + self.num_spare_cols)]
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dff_pins = [self.data_dff_insts[port].get_pin(x) for x in dff_names]
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bank_names = ["din{0}_{1}".format(port, x) for x in range(self.word_size + self.num_spare_cols)]
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bank_pins = [self.bank_inst.get_pin(x) for x in bank_names]
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route_map.extend(list(zip(bank_pins, dff_pins)))
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if port in self.readwrite_ports and OPTS.perimeter_pins:
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# outputs from sense amp
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# These are the output pins which had their pin placed on the perimeter, so route from the
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# sense amp which should not align with write driver input
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sram_names = ["dout{0}[{1}]".format(port, x) for x in range(self.word_size + self.num_spare_cols)]
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sram_pins = [self.get_pin(x) for x in sram_names]
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bank_names = ["dout{0}_{1}".format(port, x) for x in range(self.word_size + self.num_spare_cols)]
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bank_pins = [self.bank_inst.get_pin(x) for x in bank_names]
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route_map.extend(list(zip(bank_pins, sram_pins)))
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# spare wen dff
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if self.num_spare_cols > 0 and port in self.write_ports:
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dff_names = ["dout_{}".format(x) for x in range(self.num_spare_cols)]
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dff_pins = [self.spare_wen_dff_insts[port].get_pin(x) for x in dff_names]
|
|
bank_names = ["bank_spare_wen{0}_{1}".format(port, x) for x in range(self.num_spare_cols)]
|
|
bank_pins = [self.bank_inst.get_pin(x) for x in bank_names]
|
|
route_map.extend(list(zip(bank_pins, dff_pins)))
|
|
|
|
if self.num_wmasks > 0 and port in self.write_ports:
|
|
layer_stack = self.m3_stack
|
|
else:
|
|
layer_stack = self.m1_stack
|
|
|
|
if len(route_map) > 0:
|
|
if port == 0:
|
|
offset = vector(self.control_logic_insts[port].rx() + self.dff.width,
|
|
- self.data_bus_size[port] + 2 * self.m1_pitch)
|
|
import channel_route
|
|
cr = channel_route.channel_route(netlist=route_map,
|
|
offset=offset,
|
|
layer_stack=layer_stack,
|
|
parent=self)
|
|
self.add_inst("hc", cr)
|
|
self.connect_inst([])
|
|
|
|
else:
|
|
offset = vector(0,
|
|
self.bank.height + 2 * self.m1_space)
|
|
self.create_horizontal_channel_route(netlist=route_map,
|
|
offset=offset,
|
|
layer_stack=layer_stack)
|
|
|
|
def route_clk(self):
|
|
""" Route the clock network """
|
|
|
|
# This is the actual input to the SRAM
|
|
for port in self.all_ports:
|
|
# Connect all of these clock pins to the clock in the central bus
|
|
# This is something like a "spine" clock distribution. The two spines
|
|
# are clk_buf and clk_buf_bar
|
|
control_clk_buf_pin = self.control_logic_insts[port].get_pin("clk_buf")
|
|
control_clk_buf_pos = control_clk_buf_pin.center()
|
|
|
|
# This uses a metal2 track to the right (for port0) of the control/row addr DFF
|
|
# to route vertically. For port1, it is to the left.
|
|
row_addr_clk_pin = self.row_addr_dff_insts[port].get_pin("clk")
|
|
if port % 2:
|
|
control_clk_buf_pos = control_clk_buf_pin.lc()
|
|
row_addr_clk_pos = row_addr_clk_pin.lc()
|
|
mid1_pos = vector(self.row_addr_dff_insts[port].lx() - self.m2_pitch,
|
|
row_addr_clk_pos.y)
|
|
else:
|
|
control_clk_buf_pos = control_clk_buf_pin.rc()
|
|
row_addr_clk_pos = row_addr_clk_pin.rc()
|
|
mid1_pos = vector(self.row_addr_dff_insts[port].rx() + self.m2_pitch,
|
|
row_addr_clk_pos.y)
|
|
|
|
# This is the steiner point where the net branches out
|
|
clk_steiner_pos = vector(mid1_pos.x, control_clk_buf_pos.y)
|
|
self.add_path(control_clk_buf_pin.layer, [control_clk_buf_pos, clk_steiner_pos])
|
|
self.add_via_stack_center(from_layer=control_clk_buf_pin.layer,
|
|
to_layer="m2",
|
|
offset=clk_steiner_pos)
|
|
|
|
# Note, the via to the control logic is taken care of above
|
|
self.add_wire(self.m2_stack[::-1],
|
|
[row_addr_clk_pos, mid1_pos, clk_steiner_pos])
|
|
|
|
if self.col_addr_dff:
|
|
dff_clk_pin = self.col_addr_dff_insts[port].get_pin("clk")
|
|
dff_clk_pos = dff_clk_pin.center()
|
|
mid_pos = vector(clk_steiner_pos.x, dff_clk_pos.y)
|
|
self.add_wire(self.m2_stack[::-1],
|
|
[dff_clk_pos, mid_pos, clk_steiner_pos])
|
|
elif port in self.write_ports:
|
|
data_dff_clk_pin = self.data_dff_insts[port].get_pin("clk")
|
|
data_dff_clk_pos = data_dff_clk_pin.center()
|
|
mid_pos = vector(clk_steiner_pos.x, data_dff_clk_pos.y)
|
|
# In some designs, the steiner via will be too close to the mid_pos via
|
|
# so make the wire as wide as the contacts
|
|
self.add_path("m2",
|
|
[mid_pos, clk_steiner_pos],
|
|
width=max(m2_via.width, m2_via.height))
|
|
self.add_wire(self.m2_stack[::-1],
|
|
[data_dff_clk_pos, mid_pos, clk_steiner_pos])
|
|
|
|
def route_control_logic(self):
|
|
""" Route the control logic pins that are not inputs """
|
|
|
|
for port in self.all_ports:
|
|
for signal in self.control_logic_outputs[port]:
|
|
# The clock gets routed separately and is not a part of the bank
|
|
if "clk" in signal:
|
|
continue
|
|
src_pin = self.control_logic_insts[port].get_pin(signal)
|
|
dest_pin = self.bank_inst.get_pin(signal + "{}".format(port))
|
|
self.connect_vbus(src_pin, dest_pin)
|
|
|
|
for port in self.all_ports:
|
|
# Only input (besides pins) is the replica bitline
|
|
src_pin = self.control_logic_insts[port].get_pin("rbl_bl")
|
|
dest_pin = self.bank_inst.get_pin("rbl_bl{}".format(port))
|
|
self.add_wire(self.m2_stack[::-1],
|
|
[src_pin.center(), vector(src_pin.cx(), dest_pin.cy()), dest_pin.rc()])
|
|
self.add_via_stack_center(from_layer=src_pin.layer,
|
|
to_layer="m2",
|
|
offset=src_pin.center())
|
|
self.add_via_stack_center(from_layer=dest_pin.layer,
|
|
to_layer="m2",
|
|
offset=dest_pin.center())
|
|
|
|
def route_row_addr_dff(self):
|
|
""" Connect the output of the row flops to the bank pins """
|
|
for port in self.all_ports:
|
|
for bit in range(self.row_addr_size):
|
|
flop_name = "dout_{}".format(bit)
|
|
bank_name = "addr{0}_{1}".format(port, bit + self.col_addr_size)
|
|
flop_pin = self.row_addr_dff_insts[port].get_pin(flop_name)
|
|
bank_pin = self.bank_inst.get_pin(bank_name)
|
|
flop_pos = flop_pin.center()
|
|
bank_pos = bank_pin.center()
|
|
mid_pos = vector(bank_pos.x, flop_pos.y)
|
|
self.add_via_stack_center(from_layer=flop_pin.layer,
|
|
to_layer="m3",
|
|
offset=flop_pos)
|
|
self.add_path("m3", [flop_pos, mid_pos])
|
|
self.add_via_stack_center(from_layer=bank_pin.layer,
|
|
to_layer="m3",
|
|
offset=mid_pos)
|
|
self.add_path(bank_pin.layer, [mid_pos, bank_pos])
|
|
|
|
def add_lvs_correspondence_points(self):
|
|
"""
|
|
This adds some points for easier debugging if LVS goes wrong.
|
|
These should probably be turned off by default though, since extraction
|
|
will show these as ports in the extracted netlist.
|
|
"""
|
|
|
|
for n in self.control_logic_outputs[0]:
|
|
pin = self.control_logic_insts[0].get_pin(n)
|
|
self.add_label(text=n,
|
|
layer=pin.layer,
|
|
offset=pin.center())
|
|
|
|
def graph_exclude_data_dff(self):
|
|
"""Removes data dff and wmask dff (if applicable) from search graph. """
|
|
# Data dffs and wmask dffs are only for writing so are not useful for evaluating read delay.
|
|
for inst in self.data_dff_insts:
|
|
self.graph_inst_exclude.add(inst)
|
|
if self.write_size:
|
|
for inst in self.wmask_dff_insts:
|
|
self.graph_inst_exclude.add(inst)
|
|
if self.num_spare_cols:
|
|
for inst in self.spare_wen_dff_insts:
|
|
self.graph_inst_exclude.add(inst)
|
|
|
|
def graph_exclude_addr_dff(self):
|
|
"""Removes data dff from search graph. """
|
|
# Address is considered not part of the critical path, subjectively removed
|
|
for inst in self.row_addr_dff_insts:
|
|
self.graph_inst_exclude.add(inst)
|
|
|
|
if self.col_addr_dff:
|
|
for inst in self.col_addr_dff_insts:
|
|
self.graph_inst_exclude.add(inst)
|
|
|
|
def graph_exclude_ctrl_dffs(self):
|
|
"""Exclude dffs for CSB, WEB, etc from graph"""
|
|
# Insts located in control logic, exclusion function called here
|
|
for inst in self.control_logic_insts:
|
|
inst.mod.graph_exclude_dffs()
|
|
|
|
def get_sen_name(self, sram_name, port=0):
|
|
"""Returns the s_en spice name."""
|
|
# Naming scheme is hardcoded using this function, should be built into the
|
|
# graph in someway.
|
|
sen_name = "s_en{}".format(port)
|
|
control_conns = self.get_conns(self.control_logic_insts[port])
|
|
# Sanity checks
|
|
if sen_name not in control_conns:
|
|
debug.error("Signal={} not contained in control logic connections={}".format(sen_name,
|
|
control_conns))
|
|
if sen_name in self.pins:
|
|
debug.error("Internal signal={} contained in port list. Name defined by the parent.".format(sen_name))
|
|
return "X{}.{}".format(sram_name, sen_name)
|
|
|
|
def get_cell_name(self, inst_name, row, col):
|
|
"""Gets the spice name of the target bitcell."""
|
|
# Sanity check in case it was forgotten
|
|
if inst_name.find('x') != 0:
|
|
inst_name = 'x' + inst_name
|
|
return self.bank_inst.mod.get_cell_name(inst_name + '.x' + self.bank_inst.name, row, col)
|