mirror of https://github.com/VLSIDA/OpenRAM.git
611 lines
21 KiB
Python
611 lines
21 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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"""
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This is a DRC/LVS/PEX interface file for magic + netgen.
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We include the tech file for SCN4M_SUBM in the tech directory,
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that is included in OpenRAM during DRC.
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You can use this interactively by appending the magic system path in
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your .magicrc file
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path sys /Users/mrg/openram/technology/scn3me_subm/tech
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We require the version 30 Magic rules which allow via stacking.
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We obtained this file from Qflow ( http://opencircuitdesign.com/qflow/index.html )
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and include its appropriate license.
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"""
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import os
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import re
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import shutil
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import debug
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from globals import OPTS
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from .run_script import *
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# Keep track of statistics
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num_drc_runs = 0
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num_lvs_runs = 0
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num_pex_runs = 0
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# def filter_gds(cell_name, input_gds, output_gds):
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# """ Run the gds through magic for any layer processing """
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# global OPTS
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# # Copy .magicrc file into temp dir
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# magic_file = OPTS.openram_tech + "tech/.magicrc"
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# if os.path.exists(magic_file):
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# shutil.copy(magic_file, OPTS.openram_temp)
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# else:
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# debug.warning("Could not locate .magicrc file: {}".format(magic_file))
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# run_file = OPTS.openram_temp + "run_filter.sh"
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# f = open(run_file, "w")
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# f.write("#!/bin/sh\n")
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# f.write("{} -dnull -noconsole << EOF\n".format(OPTS.magic_exe[1]))
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# f.write("gds polygon subcell true\n")
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# f.write("gds warning default\n")
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# f.write("gds read {}\n".format(input_gds))
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# f.write("load {}\n".format(cell_name))
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# f.write("cellname delete \\(UNNAMED\\)\n")
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# #f.write("writeall force\n")
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# f.write("select top cell\n")
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# f.write("gds write {}\n".format(output_gds))
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# f.write("quit -noprompt\n")
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# f.write("EOF\n")
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# f.close()
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# os.system("chmod u+x {}".format(run_file))
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# (outfile, errfile, resultsfile) = run_script(cell_name, "filter")
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def write_drc_script(cell_name, gds_name, extract, final_verification, output_path, sp_name=None):
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""" Write a magic script to perform DRC and optionally extraction. """
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global OPTS
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# Copy .magicrc file into the output directory
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full_magic_file = os.environ.get('OPENRAM_MAGICRC', None)
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if not full_magic_file:
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full_magic_file = OPTS.openram_tech + "tech/.magicrc"
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if os.path.exists(full_magic_file):
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shutil.copy(full_magic_file, output_path + "/.magicrc")
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else:
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debug.warning("Could not locate .magicrc file: {}".format(full_magic_file))
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run_file = output_path + "run_ext.sh"
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f = open(run_file, "w")
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f.write("#!/bin/sh\n")
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f.write('export OPENRAM_TECH="{}"\n'.format(os.environ['OPENRAM_TECH']))
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f.write('echo "$(date): Starting GDS to MAG using Magic {}"\n'.format(OPTS.drc_exe[1]))
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f.write('\n')
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f.write("{} -dnull -noconsole << EOF\n".format(OPTS.drc_exe[1]))
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# Do not run DRC for extraction/conversion
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f.write("drc off\n")
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f.write("set VDD vdd\n")
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f.write("set GND gnd\n")
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f.write("set SUB gnd\n")
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#f.write("gds polygon subcell true\n")
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f.write("gds warning default\n")
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# Flatten the transistors
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# Bug in Netgen 1.5.194 when using this...
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try:
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from tech import blackbox_cells
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except ImportError:
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blackbox_cells = []
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try:
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from tech import flatglob
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except ImportError:
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flatglob = []
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f.write("gds readonly true\n")
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for entry in flatglob:
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f.write("gds flatglob " +entry + "\n")
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# These two options are temporarily disabled until Tim fixes a bug in magic related
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# to flattening channel routes and vias (hierarchy with no devices in it). Otherwise,
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# they appear to be disconnected.
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f.write("gds flatten true\n")
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f.write("gds ordering true\n")
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f.write("gds read {}\n".format(gds_name))
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f.write('puts "Finished reading gds {}"\n'.format(gds_name))
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f.write("load {}\n".format(cell_name))
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f.write('puts "Finished loading cell {}"\n'.format(cell_name))
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f.write("cellname delete \\(UNNAMED\\)\n")
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f.write("writeall force\n")
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# Extract
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if not sp_name:
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f.write("port makeall\n")
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else:
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f.write("readspice {}\n".format(sp_name))
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if not extract:
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pre = "#"
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else:
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pre = ""
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# Hack to work around unit scales in SkyWater
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if OPTS.tech_name=="sky130":
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f.write(pre + "extract style ngspice(si)\n")
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if final_verification and OPTS.route_supplies:
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f.write(pre + "extract unique all\n")
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f.write(pre + "extract all\n")
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f.write(pre + "select top cell\n")
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f.write(pre + "feedback why\n")
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f.write('puts "Finished extract"\n')
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# f.write(pre + "ext2spice hierarchy on\n")
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# f.write(pre + "ext2spice scale off\n")
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# lvs exists in 8.2.79, but be backword compatible for now
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# f.write(pre + "ext2spice lvs\n")
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f.write(pre + "ext2spice hierarchy on\n")
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f.write(pre + "ext2spice format ngspice\n")
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f.write(pre + "ext2spice cthresh infinite\n")
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f.write(pre + "ext2spice rthresh infinite\n")
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f.write(pre + "ext2spice renumber off\n")
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f.write(pre + "ext2spice scale off\n")
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f.write(pre + "ext2spice blackbox on\n")
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f.write(pre + "ext2spice subcircuit top on\n")
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f.write(pre + "ext2spice global off\n")
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# Can choose hspice, ngspice, or spice3,
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# but they all seem compatible enough.
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f.write(pre + "ext2spice format ngspice\n")
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f.write(pre + "ext2spice {}\n".format(cell_name))
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f.write(pre + "select top cell\n")
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f.write(pre + "feedback why\n")
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f.write('puts "Finished ext2spice"\n')
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f.write("quit -noprompt\n")
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f.write("EOF\n")
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f.write("magic_retcode=$?\n")
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f.write('echo "$(date): Finished ($magic_retcode) GDS to MAG using Magic {}"\n'.format(OPTS.drc_exe[1]))
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f.write("exit $magic_retcode\n")
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f.close()
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os.system("chmod u+x {}".format(run_file))
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run_file = output_path + "run_drc.sh"
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f = open(run_file, "w")
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f.write("#!/bin/sh\n")
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f.write('export OPENRAM_TECH="{}"\n'.format(os.environ['OPENRAM_TECH']))
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# Copy the bitcell mag files if they exist
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for blackbox_cell_name in blackbox_cells:
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mag_file = OPTS.openram_tech + "maglef_lib/" + blackbox_cell_name + ".mag"
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debug.check(os.path.isfile(mag_file), "Could not find blackbox cell {}".format(mag_file))
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f.write('cp {0} .\n'.format(mag_file))
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f.write('echo "$(date): Starting DRC using Magic {}"\n'.format(OPTS.drc_exe[1]))
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f.write('\n')
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f.write("{} -dnull -noconsole << EOF\n".format(OPTS.drc_exe[1]))
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f.write("load {} -dereference\n".format(cell_name))
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f.write('puts "Finished loading cell {}"\n'.format(cell_name))
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f.write("cellname delete \\(UNNAMED\\)\n")
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f.write("select top cell\n")
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f.write("expand\n")
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f.write('puts "Finished expanding"\n')
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f.write("drc euclidean on\n")
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f.write("drc check\n")
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f.write('puts "Finished drc check"\n')
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f.write("drc catchup\n")
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f.write('puts "Finished drc catchup"\n')
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# This is needed instead of drc count total because it displays
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# some errors that are not "DRC" errors.
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# f.write("puts -nonewline \"Total DRC errors found: \"\n")
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# f.write("puts stdout [drc listall count total]\n")
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f.write("drc count total\n")
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f.write("quit -noprompt\n")
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f.write("EOF\n")
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f.write("magic_retcode=$?\n")
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f.write('echo "$(date): Finished ($magic_retcode) DRC using Magic {}"\n'.format(OPTS.drc_exe[1]))
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f.write("exit $magic_retcode\n")
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f.close()
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os.system("chmod u+x {}".format(run_file))
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def run_drc(cell_name, gds_name, sp_name=None, extract=True, final_verification=False):
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"""Run DRC check on a cell which is implemented in gds_name."""
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global num_drc_runs
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num_drc_runs += 1
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write_drc_script(cell_name, gds_name, extract, final_verification, OPTS.openram_temp, sp_name=sp_name)
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(outfile, errfile, resultsfile) = run_script(cell_name, "ext")
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(outfile, errfile, resultsfile) = run_script(cell_name, "drc")
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# Check the result for these lines in the summary:
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# Total DRC errors found: 0
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# The count is shown in this format:
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# Cell replica_cell_6t has 3 error tiles.
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# Cell tri_gate_array has 8 error tiles.
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# etc.
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try:
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f = open(outfile, "r")
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except FileNotFoundError:
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debug.error("Unable to load DRC results file from {}. Is magic set up?".format(outfile), 1)
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results = f.readlines()
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f.close()
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errors=1
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# those lines should be the last 3
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for line in results:
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if "Total DRC errors found:" in line:
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errors = int(re.split(": ", line)[1])
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break
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else:
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debug.error("Unable to find the total error line in Magic output.", 1)
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# always display this summary
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result_str = "DRC Errors {0}\t{1}".format(cell_name, errors)
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if errors > 0:
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for line in results:
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if "error tiles" in line:
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debug.info(1, line.rstrip("\n"))
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debug.warning(result_str)
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else:
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debug.info(1, result_str)
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return errors
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def write_lvs_script(cell_name, gds_name, sp_name, final_verification=False, output_path=None):
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""" Write a netgen script to perform LVS. """
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global OPTS
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if not output_path:
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output_path = OPTS.openram_temp
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# Copy setup.tcl file into the output directory
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full_setup_file = os.environ.get('OPENRAM_NETGENRC', None)
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if not full_setup_file:
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full_setup_file = OPTS.openram_tech + "tech/setup.tcl"
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setup_file = os.path.basename(full_setup_file)
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if os.path.exists(full_setup_file):
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# Copy setup.tcl file into temp dir
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shutil.copy(full_setup_file, output_path)
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setup_file_object = open(output_path + "/setup.tcl", 'a')
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setup_file_object.write("# Increase the column sizes for ease of reading long names\n")
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setup_file_object.write("::netgen::format 120\n")
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else:
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setup_file = 'nosetup'
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run_file = output_path + "/run_lvs.sh"
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f = open(run_file, "w")
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f.write("#!/bin/sh\n")
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f.write('export OPENRAM_TECH="{}"\n'.format(os.environ['OPENRAM_TECH']))
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f.write('echo "$(date): Starting LVS using Netgen {}"\n'.format(OPTS.lvs_exe[1]))
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f.write("{} -noconsole << EOF\n".format(OPTS.lvs_exe[1]))
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# f.write("readnet spice {0}.spice\n".format(cell_name))
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# f.write("readnet spice {0}\n".format(sp_name))
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f.write("lvs {{{0}.spice {0}}} {{{1} {0}}} {2} {0}.lvs.report -full -json\n".format(cell_name, sp_name, setup_file))
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f.write("quit\n")
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f.write("EOF\n")
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f.write("magic_retcode=$?\n")
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f.write('echo "$(date): Finished ($magic_retcode) LVS using Netgen {}"\n'.format(OPTS.lvs_exe[1]))
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f.write("exit $magic_retcode\n")
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f.close()
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os.system("chmod u+x {}".format(run_file))
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def run_lvs(cell_name, gds_name, sp_name, final_verification=False, output_path=None):
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"""Run LVS check on a given top-level name which is
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implemented in gds_name and sp_name. Final verification will
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ensure that there are no remaining virtual conections. """
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global num_lvs_runs
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num_lvs_runs += 1
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if not output_path:
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output_path = OPTS.openram_temp
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write_lvs_script(cell_name, gds_name, sp_name, final_verification)
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(outfile, errfile, resultsfile) = run_script(cell_name, "lvs")
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total_errors = 0
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# check the result for these lines in the summary:
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try:
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f = open(resultsfile, "r")
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except FileNotFoundError:
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debug.error("Unable to load LVS results from {}".format(resultsfile), 1)
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results = f.readlines()
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f.close()
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# Look for the results after the final "Subcircuit summary:"
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# which will be the top-level netlist.
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final_results = []
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for line in reversed(results):
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if "Subcircuit summary:" in line:
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break
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else:
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final_results.insert(0, line)
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# There were property errors in any module.
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test = re.compile("Property errors were found.")
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propertyerrors = list(filter(test.search, results))
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total_errors += len(propertyerrors)
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# Require pins to match?
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# Cell pin lists for pnand2_1.spice and pnand2_1 altered to match.
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# test = re.compile(".*altered to match.")
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# pinerrors = list(filter(test.search, results))
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# if len(pinerrors)>0:
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# debug.warning("Pins altered to match in {}.".format(cell_name))
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#if len(propertyerrors)>0:
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# debug.warning("Property errors found, but not checking them.")
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# Netlists do not match.
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test = re.compile("Netlists do not match.")
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incorrect = list(filter(test.search, final_results))
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total_errors += len(incorrect)
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# Netlists match uniquely.
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test = re.compile("match uniquely.")
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uniquely = list(filter(test.search, final_results))
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# Netlists match uniquely.
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test = re.compile("match correctly.")
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correctly = list(filter(test.search, final_results))
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# Top level pins mismatch
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test = re.compile("The top level cell failed pin matching.")
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pins_incorrectly = list(filter(test.search, final_results))
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# Fail if the pins mismatched
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if len(pins_incorrectly) > 0:
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total_errors += 1
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# Fail if they don't match. Something went wrong!
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if len(uniquely) == 0 and len(correctly) == 0:
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total_errors += 1
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if len(uniquely) == 0 and len(correctly) > 0:
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debug.warning("{0}\tLVS matches but not uniquely".format(cell_name))
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if total_errors>0:
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# Just print out the whole file, it is short.
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for e in results:
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debug.info(1,e.strip("\n"))
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debug.error("{0}\tLVS mismatch (results in {1})".format(cell_name,
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resultsfile))
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else:
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debug.info(1, "{0}\tLVS matches".format(cell_name))
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return total_errors
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def run_pex(name, gds_name, sp_name, output=None, final_verification=False, output_path=None):
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"""Run pex on a given top-level name which is
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implemented in gds_name and sp_name. """
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global num_pex_runs
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num_pex_runs += 1
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if not output_path:
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output_path = OPTS.openram_temp
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os.chdir(output_path)
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if not output_path:
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output_path = OPTS.openram_temp
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if output == None:
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output = name + ".pex.netlist"
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# check if lvs report has been done
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# if not run drc and lvs
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if not os.path.isfile(name + ".lvs.report"):
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run_drc(name, gds_name)
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run_lvs(name, gds_name, sp_name)
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# pex_fix did run the pex using a script while dev orignial method
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# use batch mode.
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# the dev old code using batch mode does not run and is split into functions
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pex_runset = write_script_pex_rule(gds_name, name, sp_name, output)
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errfile = "{0}{1}.pex.err".format(output_path, name)
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outfile = "{0}{1}.pex.out".format(output_path, name)
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script_cmd = "{0} 2> {1} 1> {2}".format(pex_runset,
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errfile,
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outfile)
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cmd = script_cmd
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debug.info(2, cmd)
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os.system(cmd)
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# rename technology models
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pex_nelist = open(output, 'r')
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s = pex_nelist.read()
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pex_nelist.close()
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s = s.replace('pfet', 'p')
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s = s.replace('nfet', 'n')
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f = open(output, 'w')
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f.write(s)
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f.close()
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# also check the output file
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f = open(outfile, "r")
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results = f.readlines()
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f.close()
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out_errors = find_error(results)
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debug.check(os.path.isfile(output), "Couldn't find PEX extracted output.")
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correct_port(name, output, sp_name)
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return out_errors
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def write_batch_pex_rule(gds_name, name, sp_name, output):
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"""
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The dev branch old batch mode runset
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2. magic can perform extraction with the following:
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#!/bin/sh
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rm -f $1.ext
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rm -f $1.spice
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magic -dnull -noconsole << EOF
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tech load SCN3ME_SUBM.30
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#scalegrid 1 2
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gds rescale no
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gds polygon subcell true
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gds warning default
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gds read $1
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extract
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ext2spice scale off
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ext2spice
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quit -noprompt
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EOF
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"""
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pex_rules = drc["xrc_rules"]
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pex_runset = {
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'pexRulesFile': pex_rules,
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'pexRunDir': OPTS.openram_temp,
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'pexLayoutPaths': gds_name,
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'pexLayoutPrimary': name,
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#'pexSourcePath' : OPTS.openram_temp+"extracted.sp",
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'pexSourcePath': sp_name,
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'pexSourcePrimary': name,
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'pexReportFile': name + ".lvs.report",
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'pexPexNetlistFile': output,
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'pexPexReportFile': name + ".pex.report",
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'pexMaskDBFile': name + ".maskdb",
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'cmnFDIDEFLayoutPath': name + ".def",
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}
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# write the runset file
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file = OPTS.openram_temp + "pex_runset"
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f = open(file, "w")
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for k in sorted(pex_runset.keys()):
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f.write("*{0}: {1}\n".format(k, pex_runset[k]))
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f.close()
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return file
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def write_script_pex_rule(gds_name, cell_name, sp_name, output):
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global OPTS
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run_file = OPTS.openram_temp + "run_pex.sh"
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f = open(run_file, "w")
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f.write("#!/bin/sh\n")
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f.write('export OPENRAM_TECH="{}"\n'.format(os.environ['OPENRAM_TECH']))
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f.write('echo "$(date): Starting PEX using Magic {}"\n'.format(OPTS.drc_exe[1]))
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f.write("{} -dnull -noconsole << EOF\n".format(OPTS.drc_exe[1]))
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f.write("gds polygon subcell true\n")
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f.write("gds warning default\n")
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f.write("gds read {}\n".format(gds_name))
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f.write("load {}\n".format(cell_name))
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f.write("select top cell\n")
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f.write("expand\n")
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if not sp_name:
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f.write("port makeall\n")
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else:
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f.write("readspice {}\n".format(sp_name))
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f.write("extract\n")
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f.write("ext2sim labels on\n")
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f.write("ext2sim\n")
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f.write("extresist simplify off\n")
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f.write("extresist all\n")
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f.write("ext2spice hierarchy off\n")
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f.write("ext2spice format ngspice\n")
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f.write("ext2spice renumber off\n")
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f.write("ext2spice scale off\n")
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f.write("ext2spice blackbox on\n")
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f.write("ext2spice subcircuit top on\n")
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f.write("ext2spice global off\n")
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f.write("ext2spice extresist on\n")
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f.write("ext2spice {}\n".format(cell_name))
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f.write("quit -noprompt\n")
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f.write("EOF\n")
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f.write("magic_retcode=$?\n")
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f.write("mv {0}.spice {1}\n".format(cell_name, output))
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f.write('echo "$(date): Finished PEX using Magic {}"\n'.format(OPTS.drc_exe[1]))
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f.write("exit $magic_retcode\n")
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f.close()
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os.system("chmod u+x {}".format(run_file))
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return run_file
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def find_error(results):
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# Errors begin with "ERROR:"
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test = re.compile("ERROR:")
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stdouterrors = list(filter(test.search, results))
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for e in stdouterrors:
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debug.error(e.strip("\n"))
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out_errors = len(stdouterrors)
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return out_errors
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def correct_port(name, output_file_name, ref_file_name):
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pex_file = open(output_file_name, "r")
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contents = pex_file.read()
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# locate the start of circuit definition line
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match = re.search(r'^\.subckt+[^M]*', contents, re.MULTILINE)
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match_index_start = match.start()
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match_index_end = match.end()
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# store the unchanged part of pex file in memory
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pex_file.seek(0)
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part1 = pex_file.read(match_index_start)
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pex_file.seek(match_index_end)
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part2 = pex_file.read()
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bitcell_list = "+ "
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if OPTS.words_per_row:
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for bank in range(OPTS.num_banks):
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for bank in range(OPTS.num_banks):
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row = int(OPTS.num_words / OPTS.words_per_row) - 1
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col = int(OPTS.word_size * OPTS.words_per_row) - 1
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bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank, row, col)
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bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank, row, col)
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for col in range(OPTS.word_size * OPTS.words_per_row):
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for port in range(OPTS.num_r_ports + OPTS.num_w_ports + OPTS.num_rw_ports):
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bitcell_list += "bl{0}_{1} ".format(bank, col)
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bitcell_list += "br{0}_{1} ".format(bank, col)
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bitcell_list += "\n"
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control_list = "+ "
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if OPTS.words_per_row:
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for bank in range(OPTS.num_banks):
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control_list += "bank_{}/s_en0".format(bank)
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control_list += '\n'
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part2 = bitcell_list + control_list + part2
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pex_file.close()
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# obtain the correct definition line from the original spice file
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sp_file = open(ref_file_name, "r")
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contents = sp_file.read()
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circuit_title = re.search(".SUBCKT " + str(name) + ".*", contents)
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circuit_title = circuit_title.group()
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sp_file.close()
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# write the new pex file with info in the memory
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output_file = open(output_file_name, "w")
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output_file.write(part1)
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output_file.write(circuit_title + '\n')
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output_file.write(part2)
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output_file.close()
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def print_drc_stats():
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debug.info(1, "DRC runs: {0}".format(num_drc_runs))
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def print_lvs_stats():
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debug.info(1, "LVS runs: {0}".format(num_lvs_runs))
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def print_pex_stats():
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debug.info(1, "PEX runs: {0}".format(num_pex_runs))
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