Jesse Cirimelli-Low a5c879f510 Merge remote-tracking branch 'openram_local/array_gen' into merge/full-array-gen-into-dev ... # Conflicts: # technology/sky130/custom/sky130_col_cap_array.py		2026-04-30 12:43:19 -07:00
..
__init__.py	Update copyright year	2024-01-03 14:32:44 -08:00
channel_route.py	Update copyright year	2024-01-03 14:32:44 -08:00
contact.py	Merge branch 'singleport_refactor' into array_gen	2025-02-24 23:26:28 -08:00
delay_data.py	Update copyright year	2024-01-03 14:32:44 -08:00
design.py	Update copyright year	2024-01-03 14:32:44 -08:00
errors.py	Update copyright year	2024-01-03 14:32:44 -08:00
geometry.py	Merge branch 'singleport_refactor' into array_gen	2025-02-24 23:26:28 -08:00
hierarchy_design.py	Update copyright year	2024-01-03 14:32:44 -08:00
hierarchy_layout.py	Merge remote-tracking branch 'openram_local/array_gen' into merge/full-array-gen-into-dev	2026-04-30 12:43:19 -07:00
hierarchy_spice.py	Merge branch 'singleport_refactor' into array_gen	2025-02-24 23:26:28 -08:00
lef.py	Update copyright year	2024-01-03 14:32:44 -08:00
logical_effort.py	Update copyright year	2024-01-03 14:32:44 -08:00
pin_layout.py	Update copyright year	2024-01-03 14:32:44 -08:00
power_data.py	Update copyright year	2024-01-03 14:32:44 -08:00
rom_verilog.py	Update copyright year	2024-01-03 14:32:44 -08:00
route.py	Update copyright year	2024-01-03 14:32:44 -08:00
timing_graph.py	Update copyright year	2024-01-03 14:32:44 -08:00
utils.py	Update copyright year	2024-01-03 14:32:44 -08:00
vector.py	Update copyright year	2024-01-03 14:32:44 -08:00
vector3d.py	Update copyright year	2024-01-03 14:32:44 -08:00
verilog.py	Update copyright year	2024-01-03 14:32:44 -08:00
wire.py	Update copyright year	2024-01-03 14:32:44 -08:00
wire_path.py	Update copyright year	2024-01-03 14:32:44 -08:00
wire_spice_model.py	Update copyright year	2024-01-03 14:32:44 -08:00