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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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25cf57ede50c5f6f4442d907cc1d94e43cb80d1b
OpenRAM/compiler/base
T
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Matt Guthaus 25cf57ede5 Push create bus functions down into layout class.
2018-07-10 10:06:59 -07:00
..
contact.py
Consolidate metal pitch rules to new design class
2018-07-09 15:42:46 -07:00
design.py
Add new extra design class with additional hierarchy for shared design rules
2018-07-09 15:43:26 -07:00
geometry.py
Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control.
2018-03-23 08:14:09 -07:00
hierarchy_design.py
Consolidate metal pitch rules to new design class
2018-07-09 15:42:46 -07:00
hierarchy_layout.py
Push create bus functions down into layout class.
2018-07-10 10:06:59 -07:00
hierarchy_spice.py
Convert entire OpenRAM to use python3. Works with Python 3.6.
2018-05-14 16:15:45 -07:00
lef.py
Move last few modules to base dir
2018-02-09 10:29:37 -08:00
path.py
Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev
2018-02-09 10:25:28 -08:00
pin_layout.py
Convert entire OpenRAM to use python3. Works with Python 3.6.
2018-05-14 16:15:45 -07:00
route.py
Move last few modules to base dir
2018-02-09 10:29:37 -08:00
utils.py
Move utils to base.
2018-02-09 10:42:23 -08:00
vector.py
Organize top-level files into subdirs.
2018-02-09 10:25:24 -08:00
verilog.py
Move last few modules to base dir
2018-02-09 10:29:37 -08:00
wire.py
Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev
2018-02-09 10:25:28 -08:00
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