mirror of https://github.com/VLSIDA/OpenRAM.git
165 lines
6.0 KiB
Python
165 lines
6.0 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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import design
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from tech import drc, layer
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from vector import vector
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from sram_factory import factory
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from globals import OPTS
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from tech import layer_properties as layer_props
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class wordline_driver_array(design.design):
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"""
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Creates a Wordline Driver
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Generates the wordline-driver to drive the bitcell
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"""
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def __init__(self, name, rows, cols):
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super().__init__(name)
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debug.info(1, "Creating {0}".format(self.name))
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self.add_comment("rows: {0} cols: {1}".format(rows, cols))
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self.rows = rows
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self.cols = cols
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_drivers()
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def create_layout(self):
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if "li" in layer:
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self.route_layer = "li"
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else:
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self.route_layer = "m1"
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self.place_drivers()
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self.route_layout()
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self.route_vdd_gnd()
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self.offset_x_coordinates()
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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# inputs to wordline_driver.
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for i in range(self.rows):
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self.add_pin("in_{0}".format(i), "INPUT")
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# Outputs from wordline_driver.
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for i in range(self.rows):
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self.add_pin("wl_{0}".format(i), "OUTPUT")
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self.add_pin("en", "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_modules(self):
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self.wl_driver = factory.create(module_type="wordline_driver",
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cols=self.cols)
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self.add_mod(self.wl_driver)
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def route_vdd_gnd(self):
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"""
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Add a pin for each row of vdd/gnd which
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are must-connects next level up.
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"""
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if layer_props.wordline_buffer_array.vertical_supply:
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for name in ["vdd", "gnd"]:
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supply_pins = self.wld_inst[0].get_pins(name)
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for pin in supply_pins:
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self.add_layout_pin_segment_center(text=name,
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layer=pin.layer,
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start=pin.bc(),
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end=vector(pin.cx(), self.height))
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else:
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# Find the x offsets for where the vias/pins should be placed
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xoffset_list = [self.wld_inst[0].rx()]
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for num in range(self.rows):
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# this will result in duplicate polygons for rails, but who cares
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# use the inverter offset even though it will be the and's too
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(gate_offset, y_dir) = self.get_gate_offset(0,
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self.wl_driver.height,
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num)
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# Route both supplies
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for name in ["vdd", "gnd"]:
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supply_pin = self.wld_inst[num].get_pin(name)
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# Add pins in two locations
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for xoffset in xoffset_list:
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pin_pos = vector(xoffset, supply_pin.cy())
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self.add_power_pin(name, pin_pos)
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def create_drivers(self):
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self.wld_inst = []
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for row in range(self.rows):
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name_and = "wl_driver_and{}".format(row)
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# add and2
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self.wld_inst.append(self.add_inst(name=name_and,
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mod=self.wl_driver))
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self.connect_inst(["in_{0}".format(row),
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"en",
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"wl_{0}".format(row),
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"vdd", "gnd"])
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def place_drivers(self):
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for row in range(self.rows):
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if (row % 2):
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y_offset = self.wl_driver.height * (row + 1)
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inst_mirror = "MX"
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else:
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y_offset = self.wl_driver.height * row
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inst_mirror = "R0"
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and2_offset = [self.wl_driver.width, y_offset]
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# add and2
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self.wld_inst[row].place(offset=and2_offset,
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mirror=inst_mirror)
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# Leave a well gap to separate the bitcell array well from this well
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well_gap = 2 * drc("pwell_to_nwell") + drc("nwell_enclose_active")
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self.width = self.wl_driver.width + well_gap
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self.height = self.wl_driver.height * self.rows
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def route_layout(self):
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""" Route all of the signals """
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# Wordline enable connection
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en_pin = self.wld_inst[0].get_pin("B")
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en_bottom_pos = vector(en_pin.lx(), 0)
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en_pin = self.add_layout_pin(text="en",
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layer="m2",
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offset=en_bottom_pos,
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height=self.height)
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for row in range(self.rows):
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and_inst = self.wld_inst[row]
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# Drop a via
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b_pin = and_inst.get_pin("B")
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self.add_via_stack_center(from_layer=b_pin.layer,
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to_layer="m2",
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offset=b_pin.center())
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# connect the decoder input pin to and2 A
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self.copy_layout_pin(and_inst, "A", "in_{0}".format(row))
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# output each WL on the right
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wl_offset = and_inst.get_pin("Z").rc()
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self.add_layout_pin_segment_center(text="wl_{0}".format(row),
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layer=self.route_layer,
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start=wl_offset,
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end=wl_offset - vector(self.m1_width, 0))
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