mirror of https://github.com/VLSIDA/OpenRAM.git
21 lines
521 B
Python
21 lines
521 B
Python
from template import template
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dict = {
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'module_name': 'sram_1kbyte_32b_2bank',
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'bank_module_name': 'sram_1kbyte_32b_2bank_1bank',
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'vdd': 'vdd',
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'gnd': 'gnd',
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'ports': [0, 1],
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'rw_ports': [0],
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'r_ports': [1],
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'w_ports': [],
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'banks': [0, 1],
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'data_width': 32,
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'addr_width': 8,
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'bank_sel': 1,
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'num_wmask': 4
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}
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t = template('../sram/sram_multibank_template.v', dict)
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t.write(dict['module_name'] + '.v')
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