OpenRAM/compiler/pgates
mrg 0c3ee643ab Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
..
column_mux.py Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
pand2.py Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
pand3.py Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
pand4.py Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
pbuf.py Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
pbuf_dec.py Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
pdriver.py Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
pgate.py Update copyright year. 2021-01-22 11:23:28 -08:00
pinv.py Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
pinv_dec.py Update copyright year. 2021-01-22 11:23:28 -08:00
pinvbuf.py Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
pnand2.py Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
pnand3.py Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
pnand4.py Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
pnor2.py Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
precharge.py Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
ptristate_inv.py Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
ptx.py Changed delay calculation to include wire resistance and wire capacitance. Added bitline r and c values. 2021-08-01 19:25:54 -07:00
pwrite_driver.py Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
wordline_driver.py Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00