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OpenRAM/compiler/modules
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mrg 2adab1ea1a Initial work on separate delay and func simulation
2022-08-10 12:14:47 -07:00
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__init__.py
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and2_dec.py
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and3_dec.py
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and4_dec.py
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bank_select.py
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bank.py
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bitcell_1port.py
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bitcell_2port.py
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bitcell_array.py
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bitcell_base_array.py
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bitcell_base.py
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col_cap_array.py
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col_cap_bitcell_1port.py
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col_cap_bitcell_2port.py
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column_decoder.py
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column_mux_array.py
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column_mux.py
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control_logic_base.py
move most of place_instances to base
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control_logic.py
move most of place_instances to base
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delay_chain.py
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dff_array.py
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dff_buf_array.py
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dff_buf.py
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dff_inv_array.py
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dff_inv.py
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dff.py
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dummy_array.py
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dummy_bitcell_1port.py
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dummy_bitcell_2port.py
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dummy_pbitcell.py
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global_bitcell_array.py
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hierarchical_decoder.py
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hierarchical_predecode2x4.py
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hierarchical_predecode3x8.py
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hierarchical_predecode4x16.py
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hierarchical_predecode.py
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inv_dec.py
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local_bitcell_array.py
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multibank.py
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nand2_dec.py
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nand3_dec.py
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nand4_dec.py
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orig_bitcell_array.py
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pand2.py
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pand3.py
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pand4.py
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pbitcell.py
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pbuf_dec.py
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pbuf.py
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pdriver.py
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pgate.py
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pinv_dec.py
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pinv.py
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pinvbuf.py
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pnand2.py
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pnand3.py
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pnand4.py
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pnor2.py
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port_address.py
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port_data.py
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precharge_array.py
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precharge.py
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ptristate_inv.py
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ptx.py
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pwrite_driver.py
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replica_bitcell_1port.py
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replica_bitcell_2port.py
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replica_bitcell_array.py
Add fudge factor for bitcell array side rail spacings to fix DRC in freepdk45.
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replica_column.py
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replica_pbitcell.py
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row_cap_array.py
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row_cap_bitcell_1port.py
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row_cap_bitcell_2port.py
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sense_amp_array.py
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sense_amp.py
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sram_1bank.py
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sram_2bank.py
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sram_base.py
Initial work on separate delay and func simulation
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sram_config.py
Initial work on separate delay and func simulation
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sram.py
Initial work on separate delay and func simulation
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tri_gate_array.py
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tri_gate.py
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wordline_buffer_array.py
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wordline_driver_array.py
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wordline_driver.py
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write_driver_array.py
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write_driver.py
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write_mask_and_array.py
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