mirror of https://github.com/VLSIDA/OpenRAM.git
21868f9de7
Spare columns are considered as extra data bits, thus extra pins are added. However, the data bus size on the liberty file only accounted for the real data bits. This would cause pin size mismatch issues when using such macros in OpenROAD and left the whole data port disconnected. Fix it by properly setting the data bus size. Additionally, add the spare_wen pins which were also missing. |
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| .. | ||
| base | ||
| characterizer | ||
| datasheet | ||
| drc | ||
| gdsMill | ||
| model_configs | ||
| modules | ||
| router | ||
| tests | ||
| verify | ||
| Makefile | ||
| debug.py | ||
| gen_stimulus.py | ||
| globals.py | ||
| model_data_util.py | ||
| options.py | ||
| rom.py | ||
| rom_config.py | ||
| run_profile.sh | ||
| sram.py | ||
| sram_config.py | ||
| sram_factory.py | ||
| view_profile.py | ||