mirror of https://github.com/VLSIDA/OpenRAM.git
214 lines
8.8 KiB
Python
214 lines
8.8 KiB
Python
from tech import drc, parameter, cell
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import debug
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import design
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from math import log
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from math import sqrt
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import math
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from pinv import pinv
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from nand_2 import nand_2
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from vector import vector
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from globals import OPTS
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class wordline_driver(design.design):
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"""
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Creates a Wordline Driver
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Generates the wordline-driver to drive the bitcell
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"""
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def __init__(self, name, rows):
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design.design.__init__(self, name)
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self.rows = rows
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self.add_pins()
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self.design_layout()
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self.DRC_LVS()
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def add_pins(self):
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# inputs to wordline_driver.
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for i in range(self.rows):
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self.add_pin("decode_out[{0}]".format(i))
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# Outputs from wordline_driver.
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for i in range(self.rows):
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self.add_pin("wl[{0}]".format(i))
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self.add_pin("clk")
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self.add_pin("vdd")
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self.add_pin("gnd")
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def design_layout(self):
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self.add_layout()
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self.offsets_of_gates()
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self.create_layout()
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def add_layout(self):
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self.inv = pinv(name="pinverter",
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nmos_width=drc["minwidth_tx"],
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beta=parameter["pinv_beta"])
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self.add_mod(self.inv)
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self.NAND2 = nand_2(name="pnand2",
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nmos_width=2*drc["minwidth_tx"])
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self.add_mod(self.NAND2)
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def offsets_of_gates(self):
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self.x_offset0 = 2 * drc["minwidth_metal1"] + 5 * drc["metal1_to_metal1"]
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self.x_offset1 = self.x_offset0 + self.inv.width
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self.x_offset2 = self.x_offset1 + self.NAND2.width
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self.width = self.x_offset2 + self.inv.width
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self.height = self.inv.height * self.rows
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# Defining offset postions
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self.decode_out_positions = []
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self.clk_positions = []
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self.WL_positions = []
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self.vdd_positions = []
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self.gnd_positions = []
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def create_layout(self):
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# Clk connection
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self.add_rect(layer="metal1",
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offset=[drc["minwidth_metal1"] + 2 * drc["metal1_to_metal1"],
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2 * drc["minwidth_metal1"]],
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width=drc["minwidth_metal1"],
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height=self.height + 4*drc["minwidth_metal1"])
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self.clk_positions.append([drc["minwidth_metal1"] + 2*drc["metal1_to_metal1"],
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self.height])
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self.add_label(text="clk",
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layer="metal1",
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offset=self.clk_positions[0])
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for row in range(self.rows):
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name_inv1 = "Wordline_driver_inv_clk%d" % (row)
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name_nand = "Wordline_driver_nand%d" % (row)
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name_inv2 = "Wordline_driver_inv%d" % (row)
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# Extend vdd and gnd of Wordline_driver
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yoffset = (row + 1) * self.inv.height - 0.5 * drc["minwidth_metal2"]
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self.add_rect(layer="metal2",
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offset=[0, yoffset],
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width=self.x_offset0,
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height=drc["minwidth_metal2"])
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self.add_via(layers=("metal1", "via1", "metal2"),
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offset=[drc["minwidth_metal1"], yoffset],
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mirror="R90")
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self.add_via(layers=("metal1", "via1", "metal2"),
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offset=[self.x_offset0 + drc["minwidth_metal1"],
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yoffset],
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mirror="R90")
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inv_nand2B_connection_height = (abs(self.inv.Z_position.y
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- self.NAND2.B_position.y)
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+ drc["minwidth_metal1"])
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if (row % 2):
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y_offset = self.inv.height*(row + 1)
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name_inv1_offset = [self.x_offset0, y_offset]
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nand2_offset=[self.x_offset1, y_offset]
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inv2_offset=[self.x_offset2, y_offset]
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inst_mirror = "MX"
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cell_dir = vector(0,-1)
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m1tm2_rotate=270
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m1tm2_mirror="R0"
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else:
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y_offset = self.inv.height*row
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name_inv1_offset = [self.x_offset0, y_offset]
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nand2_offset=[self.x_offset1, y_offset]
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inv2_offset=[self.x_offset2, y_offset]
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inst_mirror = "R0"
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cell_dir = vector(0,1)
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m1tm2_rotate=90
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m1tm2_mirror="MX"
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# add inv1 based on the info above
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self.add_inst(name=name_inv1,
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mod=self.inv,
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offset=name_inv1_offset,
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mirror=inst_mirror )
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self.connect_inst(["clk", "clk_bar[{0}]".format(row),
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"vdd", "gnd"])
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# add nand 2
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self.add_inst(name=name_nand,
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mod=self.NAND2,
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offset=nand2_offset,
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mirror=inst_mirror)
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self.connect_inst(["decode_out[{0}]".format(row),
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"clk_bar[{0}]".format(row),
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"net[{0}]".format(row),
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"vdd", "gnd"])
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# add inv2
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self.add_inst(name=name_inv2,
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mod=self.inv,
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offset=inv2_offset,
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mirror=inst_mirror)
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self.connect_inst(["net[{0}]".format(row),
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"wl[{0}]".format(row),
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"vdd", "gnd"])
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# clk connection
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clk_offset= [drc["minwidth_metal1"] + 2 * drc["metal1_to_metal1"],
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y_offset + cell_dir.y * self.inv.A_position.y]
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self.add_rect(layer="metal1",
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offset=clk_offset,
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width=self.x_offset0 - 2*drc["metal1_to_metal1"],
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height=cell_dir.y *drc["minwidth_metal1"])
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# first inv to nand2 B
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inv_to_nand2B_offset = [self.x_offset1 - drc["minwidth_metal1"],
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y_offset + cell_dir.y * self.NAND2.B_position.y]
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self.add_rect(layer="metal1",
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offset=inv_to_nand2B_offset,
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width=drc["minwidth_metal1"],
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height=cell_dir.y*inv_nand2B_connection_height)
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# Nand2 out to 2nd inv
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nand2_to_2ndinv_offset =[self.x_offset2,
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y_offset + cell_dir.y * self.NAND2.Z_position.y]
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self.add_rect(layer="metal1",
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offset=nand2_to_2ndinv_offset,
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width=drc["minwidth_metal1"],
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height=cell_dir.y * drc["minwidth_metal1"])
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# nand2 A connection
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self.add_rect(layer="metal2",
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offset=[0, y_offset + cell_dir.y * self.NAND2.A_position.y],
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width=self.x_offset1,
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height=cell_dir.y*drc["minwidth_metal2"])
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self.add_via(layers=("metal1", "via1", "metal2"),
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offset=[self.x_offset1,
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y_offset + cell_dir.y * self.NAND2.A_position.y],
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rotate=m1tm2_rotate,
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mirror=m1tm2_mirror)
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self.add_via(layers=("metal1", "via1", "metal2"),
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offset=[0,
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y_offset +cell_dir.y*self.NAND2.A_position.y],
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mirror=inst_mirror)
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base_offset = vector(self.width, y_offset)
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decode_out_offset = base_offset.scale(0,1)+self.NAND2.A_position.scale(cell_dir)
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wl_offset = base_offset + self.inv.Z_position.scale(cell_dir)
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vdd_offset = base_offset + self.inv.vdd_position.scale(cell_dir)
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gnd_offset = base_offset + self.inv.gnd_position.scale(cell_dir)
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self.add_label(text="decode_out[{0}]".format(row),
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layer="metal2",
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offset=decode_out_offset)
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self.add_rect(layer="metal1",
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offset=wl_offset,
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width=drc["minwidth_metal1"]*cell_dir.y,
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height=drc["minwidth_metal1"]*cell_dir.y)
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self.add_label(text="wl[{0}]".format(row),
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layer="metal1",
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offset=wl_offset)
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self.add_label(text="gnd",
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layer="metal1",
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offset=gnd_offset)
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self.add_label(text="vdd",
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layer="metal1",
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offset=vdd_offset)
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self.decode_out_positions.append(decode_out_offset)
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self.WL_positions.append(wl_offset)
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self.vdd_positions.append(vdd_offset)
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self.gnd_positions.append(gnd_offset)
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