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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 01:24:39 +02:00
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1f094b03bc3f2d962ebd06138cfbade446eac82c
OpenRAM/compiler/bitcells
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mrg 3074cf3b86 Small format cleanup
2020-04-01 11:15:29 -07:00
..
bitcell_1rw_1r.py
bitcell: Remove hardcoded signal pins
2020-02-12 15:37:51 +01:00
bitcell_1w_1r.py
bitcell: Remove hardcoded signal pins
2020-02-12 15:37:51 +01:00
bitcell_base.py
Refactor bitcell to bitcell_base. Pep8 format bitcells.
2019-10-06 01:08:23 +00:00
bitcell.py
bitcell: Remove hardcoded signal pins
2020-02-12 15:37:51 +01:00
dummy_bitcell_1rw_1r.py
bitcell: Remove hardcoded signal pins
2020-02-12 15:37:51 +01:00
dummy_bitcell_1w_1r.py
bitcell: Remove hardcoded signal pins
2020-02-12 15:37:51 +01:00
dummy_bitcell.py
bitcell: Remove hardcoded signal pins
2020-02-12 15:37:51 +01:00
dummy_pbitcell.py
Add bbox for special DRC rule boundary
2019-12-05 23:14:25 +00:00
pbitcell.py
Small format cleanup
2020-04-01 11:15:29 -07:00
replica_bitcell_1rw_1r.py
bitcell: Remove hardcoded signal pins
2020-02-12 15:37:51 +01:00
replica_bitcell_1w_1r.py
bitcell: Remove hardcoded signal pins
2020-02-12 15:37:51 +01:00
replica_bitcell.py
bitcell: Remove hardcoded signal pins
2020-02-12 15:37:51 +01:00
replica_pbitcell.py
Add bbox for special DRC rule boundary
2019-12-05 23:14:25 +00:00
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