mirror of https://github.com/VLSIDA/OpenRAM.git
190 lines
7.8 KiB
Python
190 lines
7.8 KiB
Python
import debug
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import design
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from tech import drc
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from pinv import pinv
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from contact import contact
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from vector import vector
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from globals import OPTS
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class logic_effort_dc(design.design):
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"""
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Generate a logic effort based delay chain.
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Input is a list contains the electrical effort of each stage.
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"""
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def __init__(self, name, stage_list):
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"""init function"""
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design.design.__init__(self, "delay_chain")
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#fix me: input should be logic effort value
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# and there should be functions to get
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# area effecient inverter stage list
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# chain_length is number of inverters in the load
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# plus 1 for the input
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chain_length = 1 + sum(stage_list)
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# half chain length is the width of the layeout
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# invs are stacked into 2 levels so input/output are close
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half_length = round(chain_length / 2.0)
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c = reload(__import__(OPTS.config.bitcell))
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self.mod_bitcell = getattr(c, OPTS.config.bitcell)
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self.bitcell_height = self.mod_bitcell.chars["height"]
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self.add_pins()
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self.create_module()
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self.cal_cell_size(half_length)
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self.create_inv_stage_lst(stage_list)
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self.add_inv_lst(chain_length)
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self.route_inv(stage_list)
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self.add_vddgnd_label()
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self.DRC_LVS()
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def add_pins(self):
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"""add the pins of the delay chain"""
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self.add_pin("clk_in")
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self.add_pin("clk_out")
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self.add_pin("vdd")
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self.add_pin("gnd")
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def cal_cell_size(self, half_length):
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""" calculate the width and height of the cell"""
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self.width = half_length * self.inv.width
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self.height = 2 * self.bitcell_height
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def create_module(self):
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"""add the inverters"""
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self.inv = pinv(name="delay_chain_inv",
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nmos_width=drc["minwidth_tx"],
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route_output=False)
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self.add_mod(self.inv)
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def create_inv_stage_lst(self, stage_list):
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""" Generate a list to indicate what stage each inv is in """
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self.inv_stage_lst = [[0, True]]
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stage_num = 0
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for stage in stage_list:
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stage_num = stage_num + 1
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repeat_times = stage
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for i in range(repeat_times):
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if i == repeat_times - 1:
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# the first one need to connected to the next stage
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self.inv_stage_lst.append([stage_num, True])
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else:
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# the rest should not drive any thing
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self.inv_stage_lst.append([stage_num, False])
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def add_inv_lst(self, chain_length):
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"""add the inverter and connect them based on the stage list """
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half_length = round(chain_length / 2.0)
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self.inv_positions = []
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for i in range(chain_length):
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if i < half_length:
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# add top level
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inv_offset = [i * self.inv.width,
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2 * self.inv.height]
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inv_mirror="MX"
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self.inv_positions.append(inv_offset)
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offset = inv_offset + \
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self.inv.input_position.scale(1,-1)
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m1m2_via_rotate=270
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if i == 0:
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self.clk_in_offset = offset
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else:
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# add bottom level
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inv_offset = [(chain_length - i) * self.inv.width,
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0]
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inv_mirror="MY"
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self.inv_positions.append(inv_offset)
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offset = inv_offset + \
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self.inv.input_position.scale(-1,1)
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m1m2_via_rotate=90
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if i == chain_length - 1:
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self.clk_out_offset = inv_offset + \
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self.inv.output_position.scale(-1,1)
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self.add_via(layers=("metal1", "via1", "metal2"),
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offset=offset,
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rotate=m1m2_via_rotate)
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self.add_inst(name="inv_chain%d" % i,
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mod=self.inv,
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offset=inv_offset,
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mirror=inv_mirror)
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# connecting spice
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if i == 0:
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self.connect_inst(args=["clk_in", "s" + str(self.inv_stage_lst[i][0] + 1),
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"vdd", "gnd"],
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check=False)
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spare_node_counter = 1
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elif i == chain_length - 1:
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self.connect_inst(args=["s" + str(self.inv_stage_lst[i][0]), "clk_out", "vdd", "gnd"],
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check=False)
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else:
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if self.inv_stage_lst[i][1] == True:
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self.connect_inst(args=["s" + str(self.inv_stage_lst[i][0]),
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"s" + str(self.inv_stage_lst[i][0] + 1), "vdd", "gnd"],
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check=False)
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spare_node_counter = 1
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else:
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self.connect_inst(args=["s" + str(self.inv_stage_lst[i][0]), "s" \
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+ str(self.inv_stage_lst[i][0] + 1) + "n" \
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+ str(spare_node_counter), "vdd", "gnd"],
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check=False)
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spare_node_counter += 1
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def route_inv(self, stage_list):
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"""add metal routing based on the stage list """
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half_length = round((sum(stage_list) + 1) / 2.0)
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start_inv = end_inv = 0
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for stage in stage_list:
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# end inv number depends on the fan out number
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end_inv = start_inv + stage
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start_inv_offset = self.inv_positions[start_inv]
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end_inv_offset = self.inv_positions[end_inv]
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if start_inv < half_length:
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start_o_offset = start_inv_offset + \
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self.inv.output_position.scale(1,-1)
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m1m2_via_rotate =270
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m1m2_via_vc = vector(1,-.5)
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else:
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start_o_offset = start_inv_offset + \
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self.inv.output_position.scale(-1,1)
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m1m2_via_rotate =90
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m1m2_via_vc = vector(1,.5)
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M2_start = start_o_offset + vector(0,drc["minwidth_metal2"]).scale(m1m2_via_vc)
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self.add_via(layers=("metal1", "via1", "metal2"),
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offset=start_o_offset,
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rotate=m1m2_via_rotate)
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if end_inv < half_length:
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end_i_offset = end_inv_offset + \
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self.inv.input_position.scale(1,-1)
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M2_end = end_i_offset - vector(0, 0.5 * drc["minwidth_metal2"])
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else:
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end_i_offset = end_inv_offset + \
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self.inv.input_position.scale(-1,1)
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M2_end = end_i_offset + vector(0, 0.5 * drc["minwidth_metal2"])
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if start_inv < half_length and end_inv >= half_length:
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mid = [half_length * self.inv.width \
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- 0.5 * drc["minwidth_metal2"], M2_start[1]]
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self.add_wire(("metal2", "via2", "metal3"),
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[M2_start, mid, M2_end])
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else:
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self.add_path(("metal2"), [M2_start, M2_end])
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# set the start of next one after current end
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start_inv = end_inv
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def add_vddgnd_label(self):
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"""add vdd and gnd labels"""
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for i in range(3):
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if i % 2:
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self.add_label(text="vdd",
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layer="metal1",
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offset=[0, i * self.bitcell_height])
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else:
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self.add_label(text="gnd",
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layer="metal1",
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offset=[0, i * self.bitcell_height])
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