mirror of https://github.com/VLSIDA/OpenRAM.git
24 lines
683 B
Python
24 lines
683 B
Python
import design
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import debug
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import utils
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from tech import GDS,layer
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class bitcell(design.design):
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"""
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A single bit cell (6T, 8T, etc.) This module implements the
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single memory cell used in the design. It is a hand-made cell, so
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the layout and netlist should be available in the technology
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library.
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"""
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pins = ["BL", "BR", "WL", "vdd", "gnd"]
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chars = utils.auto_measure_libcell(pins, "cell_6t", GDS["unit"], layer["boundary"])
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def __init__(self, name="cell_6t"):
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design.design.__init__(self, name)
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debug.info(2, "Create bitcell object")
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self.width = bitcell.chars["width"]
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self.height = bitcell.chars["height"]
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