mirror of https://github.com/VLSIDA/OpenRAM.git
87 lines
3.1 KiB
Python
87 lines
3.1 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import design
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from tech import spice, parameter, drc
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from tech import cell_properties as props
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import logical_effort
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class nand3_dec(design.design):
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"""
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3-input NAND decoder for address decoders.
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"""
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def __init__(self, name="nand3_dec", height=None):
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super().__init__(name, prop=props.nand3_dec)
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# FIXME: For now...
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size = 1
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self.size = size
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self.nmos_size = 2 * size
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self.pmos_size = parameter["beta"] * size
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self.nmos_width = self.nmos_size * drc("minwidth_tx")
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self.pmos_width = self.pmos_size * drc("minwidth_tx")
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def analytical_power(self, corner, load):
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"""Returns dynamic and leakage power. Results in nW"""
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c_eff = self.calculate_effective_capacitance(load)
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freq = spice["default_event_frequency"]
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power_dyn = self.calc_dynamic_power(corner, c_eff, freq)
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power_leak = spice["nand3_leakage"]
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total_power = self.return_power(power_dyn, power_leak)
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return total_power
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def calculate_effective_capacitance(self, load):
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"""Computes effective capacitance. Results in fF"""
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c_load = load
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# In fF
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c_para = spice["min_tx_drain_c"] * (self.nmos_size / parameter["min_tx_size"])
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transition_prob = 0.1875
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return transition_prob * (c_load + c_para)
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def input_load(self):
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"""Return the relative input capacitance of a single input"""
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return self.nmos_size + self.pmos_size
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def get_stage_effort(self, cout, inp_is_rise=True):
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"""
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Returns an object representing the parameters for delay in tau units.
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Optional is_rise refers to the input direction rise/fall.
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Input inverted by this stage.
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"""
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parasitic_delay = 2
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return logical_effort.logical_effort(self.name,
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self.size,
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self.input_load(),
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cout,
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parasitic_delay,
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not inp_is_rise)
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def build_graph(self, graph, inst_name, port_nets):
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"""
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Adds edges based on inputs/outputs.
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Overrides base class function.
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"""
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self.add_graph_edges(graph, port_nets)
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def is_non_inverting(self):
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"""Return input to output polarity for module"""
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return False
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def get_on_resistance(self):
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"""On resistance of pnand, defined by stacked NMOS"""
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is_nchannel = True
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stack = 3
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is_cell = False
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return self.tr_r_on(self.nmos_width, is_nchannel, stack, is_cell)
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def get_input_capacitance(self):
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"""Input cap of input, passes width of gates to gate cap function"""
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return self.gate_c(self.nmos_width+self.pmos_width) |