mirror of https://github.com/VLSIDA/OpenRAM.git
263 lines
11 KiB
Python
263 lines
11 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import contact
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import pgate
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import debug
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from tech import drc, parameter, spice
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from vector import vector
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from sram_factory import factory
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class pnor2(pgate.pgate):
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"""
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This module generates gds of a parametrically sized 2-input nor.
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This model use ptx to generate a 2-input nor within a cetrain height.
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"""
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def __init__(self, name, size=1, height=None):
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""" Creates a cell for a simple 2 input nor """
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debug.info(2,
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"creating pnor2 structure {0} with size of {1}".format(name,
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size))
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self.add_comment("size: {}".format(size))
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self.nmos_size = size
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# We will just make this 1.5 times for now. NORs are not ideal anyhow.
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self.pmos_size = 1.5 * parameter["beta"] * size
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self.nmos_width = self.nmos_size * drc("minwidth_tx")
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self.pmos_width = self.pmos_size * drc("minwidth_tx")
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# FIXME: Allow these to be sized
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debug.check(size==1, "Size 1 pnor2 is only supported now.")
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self.tx_mults = 1
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# Creates the netlist and layout
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pgate.pgate.__init__(self, name, height)
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def create_netlist(self):
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self.add_pins()
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self.add_ptx()
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self.create_ptx()
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def create_layout(self):
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""" Calls all functions related to the generation of the layout """
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self.setup_layout_constants()
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self.route_supply_rails()
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self.place_ptx()
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self.connect_rails()
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self.add_well_contacts()
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self.extend_wells(self.well_pos)
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self.route_inputs()
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self.route_output()
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def add_pins(self):
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""" Adds pins for spice netlist """
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pin_list = ["A", "B", "Z", "vdd", "gnd"]
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dir_list = ["INPUT", "INPUT", "OUTPUT", "INOUT", "INOUT"]
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self.add_pin_list(pin_list, dir_list)
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def add_ptx(self):
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""" Create the PMOS and NMOS transistors. """
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self.nmos = factory.create(module_type="ptx",
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width=self.nmos_width,
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mults=self.tx_mults,
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tx_type="nmos",
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connect_poly=True,
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connect_active=True)
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self.add_mod(self.nmos)
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self.pmos = factory.create(module_type="ptx",
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width=self.pmos_width,
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mults=self.tx_mults,
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tx_type="pmos",
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connect_poly=True,
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connect_active=True)
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self.add_mod(self.pmos)
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def setup_layout_constants(self):
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""" Pre-compute some handy layout parameters. """
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# metal spacing to allow contacts on any layer
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self.input_spacing = max(self.poly_space + contact.poly.first_layer_width,
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self.m1_space + contact.m1m2.first_layer_width,
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self.m2_space + contact.m2m3.first_layer_width,
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self.m3_space + contact.m2m3.second_layer_width)
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# Compute the other pmos2 location, but determining
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# offset to overlap the source and drain pins
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self.overlap_offset = self.pmos.get_pin("D").ll() - self.pmos.get_pin("S").ll()
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# Two PMOS devices and a well contact. Separation between each.
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# Enclosure space on the sides.
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self.well_width = 2 * self.pmos.active_width \
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+ self.pmos.active_contact.width \
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+ 2 * drc("active_to_body_active") \
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+ 2 * drc("well_enclosure_active")
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self.width = self.well_width
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# Height is an input parameter, so it is not recomputed.
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# This is the extra space needed to ensure DRC rules
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# to the active contacts
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extra_contact_space = max(-self.nmos.get_pin("D").by(), 0)
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# This is a poly-to-poly of a flipped cell
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self.top_bottom_space = max(0.5 * self.m1_width + self.m1_space + extra_contact_space,
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drc("poly_extend_active"),
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self.poly_space)
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def route_supply_rails(self):
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""" Add vdd/gnd rails to the top and bottom. """
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self.add_layout_pin_rect_center(text="gnd",
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layer="metal1",
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offset=vector(0.5 * self.width, 0),
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width=self.width)
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self.add_layout_pin_rect_center(text="vdd",
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layer="metal1",
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offset=vector(0.5 * self.width, self.height),
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width=self.width)
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def create_ptx(self):
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"""
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Add PMOS and NMOS to the layout at the upper-most and lowest position
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to provide maximum routing in channel
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"""
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self.pmos1_inst = self.add_inst(name="pnor2_pmos1",
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mod=self.pmos)
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self.connect_inst(["vdd", "A", "net1", "vdd"])
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self.pmos2_inst = self.add_inst(name="pnor2_pmos2",
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mod=self.pmos)
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self.connect_inst(["net1", "B", "Z", "vdd"])
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self.nmos1_inst = self.add_inst(name="pnor2_nmos1",
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mod=self.nmos)
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self.connect_inst(["Z", "A", "gnd", "gnd"])
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self.nmos2_inst = self.add_inst(name="pnor2_nmos2",
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mod=self.nmos)
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self.connect_inst(["Z", "B", "gnd", "gnd"])
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def place_ptx(self):
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"""
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Add PMOS and NMOS to the layout at the upper-most and lowest position
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to provide maximum routing in channel
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"""
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pmos1_pos = vector(self.pmos.active_offset.x,
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self.height - self.pmos.active_height \
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- self.top_bottom_space)
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self.pmos1_inst.place(pmos1_pos)
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self.pmos2_pos = pmos1_pos + self.overlap_offset
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self.pmos2_inst.place(self.pmos2_pos)
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nmos1_pos = vector(self.pmos.active_offset.x, self.top_bottom_space)
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self.nmos1_inst.place(nmos1_pos)
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self.nmos2_pos = nmos1_pos + self.overlap_offset
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self.nmos2_inst.place(self.nmos2_pos)
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# Output position will be in between the PMOS and NMOS
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self.output_pos = vector(0,
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0.5 * (pmos1_pos.y + nmos1_pos.y + self.nmos.active_height))
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# This will help with the wells
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self.well_pos = vector(0, self.nmos1_inst.uy())
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def add_well_contacts(self):
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""" Add n/p well taps to the layout and connect to supplies """
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self.add_nwell_contact(self.pmos, self.pmos2_pos)
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self.add_pwell_contact(self.nmos, self.nmos2_pos)
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def connect_rails(self):
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""" Connect the nmos and pmos to its respective power rails """
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self.connect_pin_to_rail(self.nmos1_inst, "S", "gnd")
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self.connect_pin_to_rail(self.nmos2_inst, "D", "gnd")
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self.connect_pin_to_rail(self.pmos1_inst, "S", "vdd")
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def route_inputs(self):
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""" Route the A and B inputs """
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# Use M2 spaces so we can drop vias on the pins later!
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inputB_yoffset = self.nmos2_pos.y + self.nmos.active_height \
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+ self.m2_space + self.m2_width
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self.route_input_gate(self.pmos2_inst,
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self.nmos2_inst,
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inputB_yoffset,
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"B",
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position="center")
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# This will help with the wells and the input/output placement
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self.inputA_yoffset = inputB_yoffset + self.input_spacing
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self.route_input_gate(self.pmos1_inst,
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self.nmos1_inst,
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self.inputA_yoffset,
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"A")
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def route_output(self):
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""" Route the Z output """
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# PMOS2 drain
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pmos_pin = self.pmos2_inst.get_pin("D")
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# NMOS1 drain
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nmos_pin = self.nmos1_inst.get_pin("D")
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# NMOS2 drain (for output via placement)
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nmos2_pin = self.nmos2_inst.get_pin("D")
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# Go up to metal2 for ease on all output pins
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=pmos_pin.center())
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m1m2_contact = self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=nmos_pin.center())
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mid1_offset = vector(pmos_pin.center().x, nmos2_pin.center().y)
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mid2_offset = vector(pmos_pin.center().x, self.inputA_yoffset)
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mid3_offset = mid2_offset + vector(self.m2_width, 0)
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# PMOS1 to mid-drain to NMOS2 drain
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self.add_path("metal2",
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[pmos_pin.bc(), mid2_offset, mid3_offset])
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self.add_path("metal2",
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[nmos_pin.rc(), mid1_offset, mid2_offset])
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# This extends the output to the edge of the cell
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=mid3_offset)
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self.add_layout_pin_rect_center(text="Z",
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layer="metal1",
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offset=mid3_offset,
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width=contact.m1m2.first_layer_height,
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height=contact.m1m2.first_layer_width)
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def analytical_power(self, corner, load):
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"""Returns dynamic and leakage power. Results in nW"""
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c_eff = self.calculate_effective_capacitance(load)
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freq = spice["default_event_frequency"]
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power_dyn = self.calc_dynamic_power(corner, c_eff, freq)
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power_leak = spice["nor2_leakage"]
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total_power = self.return_power(power_dyn, power_leak)
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return total_power
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def calculate_effective_capacitance(self, load):
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"""Computes effective capacitance. Results in fF"""
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c_load = load
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# In fF
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c_para = spice["min_tx_drain_c"] * (self.nmos_size / parameter["min_tx_size"])
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transition_prob = 0.1875
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return transition_prob * (c_load + c_para)
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def build_graph(self, graph, inst_name, port_nets):
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"""Adds edges based on inputs/outputs. Overrides base class function."""
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self.add_graph_edges(graph, port_nets)
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