mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-04 16:51:40 +02:00
Bastian Koppelmann
df9f351a91
this is technology specific database to store data about the custom design cells. For now it only contains on which axis the bitcells are mirrored. This is a first step to support thin cells that need to be mirrored on the x and y axis. Signed-off-by: Bastian Koppelmann <[email protected]>
307 lines
11 KiB
Python
Executable File
307 lines
11 KiB
Python
Executable File
import os
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from design_rules import *
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from module_type import *
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from custom_cell_properties import CellProperties
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"""
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File containing the process technology parameters for SCMOS 3me, subm, 180nm.
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"""
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# This uses the default classes to instantiate module from
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# '$OPENRAM_HOME/compiler/modules'.
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# Using tech_modules['cellname'] you can override each class by providing a custom
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# implementation in '$OPENRAM_TECHDIR/modules/'
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# For example: tech_modules['contact'] = 'contact_scn3me'
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tech_modules = ModuleType()
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###################################################
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# Custom cell properties
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###################################################
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cell_properties = CellProperties()
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cell_properties.bitcell.mirror.x = True
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cell_properties.bitcell.mirror.y = False
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#GDS file info
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GDS={}
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# gds units
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# gds units
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# From http://www.cnf.cornell.edu/cnf_spie9.html: "The first
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#is the size of a database unit in user units. The second is the size
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#of a database unit in meters. For example, if your library was
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#created with the default units (user unit = 1 m and 1000 database
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#units per user unit), then the first number would be 0.001 and the
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#second number would be 10-9. Typically, the first number is less than
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#1, since you use more than 1 database unit per user unit. To
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#calculate the size of a user unit in meters, divide the second number
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#by the first."
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GDS["unit"]=(0.001,1e-6)
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# default label zoom
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GDS["zoom"] = 0.5
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###################################################
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##GDS Layer Map
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###################################################
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# create the GDS layer map
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layer={}
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layer["vtg"] = (-1, 0)
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layer["vth"] = (-1, 0)
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layer["contact"] = (47, 0)
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layer["pwell"] = (41, 0)
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layer["nwell"] = (42, 0)
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layer["active"] = (43, 0)
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layer["pimplant"] = (44, 0)
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layer["nimplant"] = (45, 0)
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layer["poly"] = (46, 0)
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layer["active_contact"] = (48, 0)
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layer["metal1"] = (49, 0)
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layer["via1"] = (50, 0)
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layer["metal2"] = (51, 0)
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layer["via2"] = (61, 0)
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layer["metal3"] = (62, 0)
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layer["text"] = (63, 0)
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layer["boundary"] = (63, 0)
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layer["blockage"] = (83, 0)
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###################################################
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##END GDS Layer Map
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###################################################
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###################################################
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##DRC/LVS Rules Setup
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###################################################
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_lambda_ = 0.3
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#technology parameter
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parameter={}
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parameter["min_tx_size"] = 4*_lambda_
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parameter["beta"] = 2
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parameter["6T_inv_nmos_size"] = 8*_lambda_
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parameter["6T_inv_pmos_size"] = 3*_lambda_
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parameter["6T_access_size"] = 4*_lambda_
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drclvs_home=os.environ.get("DRCLVS_HOME")
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drc = design_rules("scn3me_subm")
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drc["body_tie_down"] = 0
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drc["has_pwell"] = True
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drc["has_nwell"] = True
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#grid size is 1/2 a lambda
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drc["grid"]=0.5*_lambda_
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#DRC/LVS test set_up
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drc["drc_rules"]=drclvs_home+"/calibreDRC_scn3me_subm.rul"
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drc["lvs_rules"]=drclvs_home+"/calibreLVS_scn3me_subm.rul"
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drc["layer_map"]=os.environ.get("OPENRAM_TECH")+"/scn3me_subm/layers.map"
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# minwidth_tx with contact (no dog bone transistors)
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drc["minwidth_tx"] = 4*_lambda_
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drc["minlength_channel"] = 2*_lambda_
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# 1.3 Minimum spacing between wells of same type (if both are drawn)
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drc["well_to_well"] = 6*_lambda_
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# 1.4 Minimum spacing between wells of different type (if both are drawn)
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drc["pwell_to_nwell"] = 0
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# 1.1 Minimum width
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drc["minwidth_well"] = 12*_lambda_
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# 3.1 Minimum width
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drc["minwidth_poly"] = 2*_lambda_
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# 3.2 Minimum spacing over active
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drc["poly_to_poly"] = 3*_lambda_
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# 3.3 Minimum gate extension of active
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drc["poly_extend_active"] = 2*_lambda_
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# 5.5.b Minimum spacing between poly contact and other poly (alternative rules)
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drc["poly_to_polycontact"] = 4*_lambda_
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# ??
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drc["active_enclosure_gate"] = 0.0
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# 3.5 Minimum field poly to active
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drc["poly_to_active"] = _lambda_
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# 3.2.a Minimum spacing over field poly
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drc["poly_to_field_poly"] = 3*_lambda_
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# Not a rule
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drc["minarea_poly"] = 0.0
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# ??
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drc["active_to_body_active"] = 4*_lambda_ # Fix me
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# 2.1 Minimum width
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drc["minwidth_active"] = 3*_lambda_
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# 2.2 Minimum spacing
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drc["active_to_active"] = 3*_lambda_
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# 2.3 Source/drain active to well edge
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drc["well_enclosure_active"] = 6*_lambda_
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# Reserved for asymmetric enclosures
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drc["well_extend_active"] = 6*_lambda_
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# Not a rule
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drc["minarea_active"] = 0.0
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# 4.1 Minimum select spacing to channel of transistor to ensure adequate source/drain width
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drc["implant_to_channel"] = 3*_lambda_
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# 4.2 Minimum select overlap of active
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drc["implant_enclosure_active"] = 2*_lambda_
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# 4.3 Minimum select overlap of contact
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drc["implant_enclosure_contact"] = _lambda_
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# Not a rule
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drc["implant_to_contact"] = 0
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# Not a rule
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drc["implant_to_implant"] = 0
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# Not a rule
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drc["minwidth_implant"] = 0
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# 6.1 Exact contact size
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drc["minwidth_contact"] = 2*_lambda_
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# 5.3 Minimum contact spacing
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drc["contact_to_contact"] = 3*_lambda_
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# 6.2.b Minimum active overlap
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drc["active_enclosure_contact"] = _lambda_
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# Reserved for asymmetric enclosure
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drc["active_extend_contact"] = _lambda_
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# 5.2.b Minimum poly overlap
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drc["poly_enclosure_contact"] = _lambda_
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# Reserved for asymmetric enclosures
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drc["poly_extend_contact"] = _lambda_
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# Reserved for other technologies
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drc["contact_to_gate"] = 2*_lambda_
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# 5.4 Minimum spacing to gate of transistor
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drc["contact_to_poly"] = 2*_lambda_
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# 7.1 Minimum width
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drc["minwidth_metal1"] = 3*_lambda_
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# 7.2 Minimum spacing
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drc["metal1_to_metal1"] = 3*_lambda_
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# 7.3 Minimum overlap of any contact
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drc["metal1_enclosure_contact"] = _lambda_
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# Reserved for asymmetric enclosure
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drc["metal1_extend_contact"] = _lambda_
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# 8.3 Minimum overlap by metal1
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drc["metal1_enclosure_via1"] = _lambda_
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# Reserve for asymmetric enclosures
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drc["metal1_extend_via1"] = _lambda_
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# Not a rule
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drc["minarea_metal1"] = 0
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# 8.1 Exact size
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drc["minwidth_via1"] = 2*_lambda_
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# 8.2 Minimum via1 spacing
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drc["via1_to_via1"] = 3*_lambda_
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# 9.1 Minimum width
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drc["minwidth_metal2"] = 3*_lambda_
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# 9.2 Minimum spacing
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drc["metal2_to_metal2"] = 3*_lambda_
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# 9.3 Minimum overlap of via1
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drc["metal2_extend_via1"] = _lambda_
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# Reserved for asymmetric enclosures
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drc["metal2_enclosure_via1"] = _lambda_
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# 14.3 Minimum overlap by metal2
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drc["metal2_extend_via2"] = _lambda_
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# Reserved for asymmetric enclosures
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drc["metal2_enclosure_via2"] = _lambda_
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# Not a rule
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drc["minarea_metal2"] = 0
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# 14.1 Exact size
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drc["minwidth_via2"] = 2*_lambda_
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# 14.2 Minimum spacing
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drc["via2_to_via2"] = 3*_lambda_
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# 15.1 Minimum width
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drc["minwidth_metal3"] = 5*_lambda_
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# 15.2 Minimum spacing to metal3
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drc["metal3_to_metal3"] = 3*_lambda_
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# 15.3 Minimum overlap of via 2
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drc["metal3_extend_via2"] = 2*_lambda_
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# Reserved for asymmetric enclosures
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drc["metal3_enclosure_via2"] = 2*_lambda_
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# Not a rule
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drc["minarea_metal3"] = 0
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###################################################
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##END DRC/LVS Rules
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###################################################
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###################################################
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##Spice Simulation Parameters
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###################################################
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# spice model info
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spice={}
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spice["nmos"]="n"
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spice["pmos"]="p"
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# This is a map of corners to model files
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SPICE_MODEL_DIR=os.environ.get("SPICE_MODEL_DIR")
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spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"],
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"FF" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/ff/nmos.sp"],
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"FS" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/ss/nmos.sp"],
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"SF" : [SPICE_MODEL_DIR+"/ss/pmos.sp",SPICE_MODEL_DIR+"/ff/nmos.sp"],
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"SS" : [SPICE_MODEL_DIR+"/ss/pmos.sp",SPICE_MODEL_DIR+"/ss/nmos.sp"],
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"ST" : [SPICE_MODEL_DIR+"/ss/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"],
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"TS" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/ss/nmos.sp"],
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"FT" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"],
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"TF" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/ff/nmos.sp"],
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}
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#spice stimulus related variables
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spice["feasible_period"] = 10 # estimated feasible period in ns
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spice["supply_voltages"] = [4.5, 5.0, 5.5] # Supply voltage corners in [Volts]
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spice["nom_supply_voltage"] = 5.0 # Nominal supply voltage in [Volts]
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spice["rise_time"] = 0.05 # rise time in [Nano-seconds]
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spice["fall_time"] = 0.05 # fall time in [Nano-seconds]
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spice["temperatures"] = [0, 25, 100] # Temperature corners (celcius)
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spice["nom_temperature"] = 25 # Nominal temperature (celcius)
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# analytical delay parameters
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spice["nom_threshold"] = 1.3 # Typical Threshold voltage in Volts
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# FIXME: These need to be updated for SCMOS, they are copied from FreePDK45.
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spice["wire_unit_r"] = 0.075 # Unit wire resistance in ohms/square
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spice["wire_unit_c"] = 0.64 # Unit wire capacitance ff/um^2
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spice["min_tx_drain_c"] = 0.7 # Minimum transistor drain capacitance in ff
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spice["min_tx_gate_c"] = 0.1 # Minimum transistor gate capacitance in ff
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spice["dff_setup"] = 9 # DFF setup time in ps
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spice["dff_hold"] = 1 # DFF hold time in ps
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spice["dff_in_cap"] = 9.8242 # Input capacitance (D) [Femto-farad]
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spice["dff_out_cap"] = 2 # Output capacitance (Q) [Femto-farad]
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# analytical power parameters, many values are temporary
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spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nW
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spice["inv_leakage"] = 1 # Leakage power of inverter in nW
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spice["nand2_leakage"] = 1 # Leakage power of 2-input nand in nW
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spice["nand3_leakage"] = 1 # Leakage power of 3-input nand in nW
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spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW
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spice["dff_leakage"] = 1 # Leakage power of flop in nW
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spice["default_event_frequency"] = 100 # Default event activity of every gate. MHz
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#Logical Effort relative values for the Handmade cells
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parameter["le_tau"] = 23 #In pico-seconds.
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parameter["min_inv_para_delay"] = 0.73 #In relative delay units
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parameter["cap_relative_per_ff"] = 0.91 #Units of Relative Capacitance/ Femto-Farad
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parameter["dff_clk_cin"] = 27.5 #In relative capacitance units
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parameter["6tcell_wl_cin"] = 2 #In relative capacitance units
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parameter["sa_en_pmos_size"] = 24*_lambda_
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parameter["sa_en_nmos_size"] = 9*_lambda_
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parameter["sa_inv_pmos_size"] = 18*_lambda_
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parameter["sa_inv_nmos_size"] = 9*_lambda_
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parameter["bitcell_drain_cap"] = 0.2 #In Femto-Farad, approximation of drain capacitance
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###################################################
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##END Spice Simulation Parameters
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###################################################
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###################################################
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##BEGIN Technology Tool Preferences
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###################################################
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drc_name = "magic"
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lvs_name = "netgen"
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pex_name = "magic"
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###################################################
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##END Technology Tool Preferences
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###################################################
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