mirror of https://github.com/VLSIDA/OpenRAM.git
50 lines
1.3 KiB
Python
50 lines
1.3 KiB
Python
#!/usr/bin/env python2.7
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"""
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Check the .v file for an SRAM
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"""
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import unittest
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from testutils import header,openram_test
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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class verilog_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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# we will manually run lvs/drc
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OPTS.check_lvsdrc = False
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import sram
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debug.info(1, "Testing Verilog for sample 2 bit, 16 words SRAM with 1 bank")
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s = sram.sram(word_size=2,
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num_words=OPTS.num_words,
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num_banks=OPTS.num_banks,
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name="sram_2_16_1_{0}".format(OPTS.tech_name))
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OPTS.check_lvsdrc = True
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vfile = s.name + ".v"
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vname = OPTS.openram_temp + vfile
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s.verilog_write(vname)
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# let's diff the result with a golden model
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golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),vfile)
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self.isdiff(vname,golden)
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os.system("rm {0}".format(vname))
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globals.end_openram()
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# instantiate a copdsay of the class to actually run the test
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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