mirror of https://github.com/VLSIDA/OpenRAM.git
111 lines
4.0 KiB
Python
111 lines
4.0 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California
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# All rights reserved.
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#
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from bitcell_base_array import bitcell_base_array
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from sram_factory import factory
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from globals import OPTS
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from tech import cell_properties
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class col_cap_array(bitcell_base_array):
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"""
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Generate a dummy row/column for the replica array.
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"""
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def __init__(self, rows, cols, column_offset=0, mirror=0, location="", name=""):
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super().__init__(rows=rows, cols=cols, column_offset=column_offset, name=name)
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self.mirror = mirror
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self.location = location
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self.no_instances = True
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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""" Create and connect the netlist """
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# This will create a default set of bitline/wordline names
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try:
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end_caps_enabled = cell_properties.bitcell.end_caps
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except AttributeError:
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end_caps_enabled = False
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if not end_caps_enabled:
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self.create_all_wordline_names()
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self.create_all_bitline_names()
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.place_array("dummy_r{0}_c{1}", self.mirror)
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def add_modules(self):
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""" Add the modules used in this design """
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self.dummy_cell = factory.create(module_type="col_cap_{}".format(OPTS.bitcell))
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self.add_mod(self.dummy_cell)
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self.cell = factory.create(module_type="bitcell")
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def create_instances(self):
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""" Create the module instances used in this design """
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self.cell_inst = {}
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for col in range(self.column_size):
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for row in range(self.row_size):
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name = "bit_r{0}_c{1}".format(row, col)
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self.cell_inst[row, col]=self.add_inst(name=name,
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mod=self.dummy_cell)
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self.connect_inst(self.get_bitcell_pins(row, col))
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def get_bitcell_pins(self, row, col):
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"""
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Creates a list of connections in the bitcell,
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indexed by column and row, for instance use in bitcell_array
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"""
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if len(self.all_ports) == 1:
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pin_name = cell_properties.bitcell.cell_6t.pin
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bitcell_pins = ["{0}_{1}".format(pin_name.bl0, col),
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"{0}_{1}".format(pin_name.br0, col),
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"vdd"]
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else:
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pin_name = cell_properties.bitcell.cell_1rw1r.pin
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bitcell_pins = ["{0}_{1}".format(pin_name.bl0, col),
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"{0}_{1}".format(pin_name.br0, col),
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"{0}_{1}".format(pin_name.bl1, col),
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"{0}_{1}".format(pin_name.br1, col),
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"vdd"]
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return bitcell_pins
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def add_layout_pins(self):
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""" Add the layout pins """
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column_list = self.cell.get_all_bitline_names()
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for col in range(self.column_size):
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for cell_column in column_list:
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bl_pin = self.cell_inst[0, col].get_pin(cell_column)
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self.add_layout_pin(text=cell_column + "_{0}".format(col),
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layer=bl_pin.layer,
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offset=bl_pin.ll().scale(1, 0),
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width=bl_pin.width(),
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height=self.height)
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# Add vdd/gnd via stacks
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for row in range(self.row_size):
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for col in range(self.column_size):
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inst = self.cell_inst[row, col]
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for pin_name in ["vdd", "gnd"]:
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for pin in inst.get_pins(pin_name):
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self.add_power_pin(name=pin.name,
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loc=pin.center(),
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start_layer=pin.layer)
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