luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
1624d50ca9c82dabdc4b667c57aadc23910360c0
OpenRAM/compiler/example_configs
T
History
mrg 2f12c77668 Create single port memory config examples.
2020-11-03 14:42:56 -08:00
..
big_config_scn4m_subm.py
Fixed nominal_corner_only parameter.
2020-10-30 15:52:07 -07:00
example_config_1rw_1r_scn4m_subm.py
Fixed nominal_corner_only parameter.
2020-10-30 15:52:07 -07:00
example_config_1rw_1w_scn4m_subm.py
Fixed nominal_corner_only parameter.
2020-10-30 15:52:07 -07:00
example_config_1rw_2mux_scn4m_subm.py
Fixed nominal_corner_only parameter.
2020-10-30 15:52:07 -07:00
example_config_1w_1r_scn4m_subm.py
Fixed nominal_corner_only parameter.
2020-10-30 15:52:07 -07:00
example_config_2rw_scn4m_subm.py
Fixed nominal_corner_only parameter.
2020-10-30 15:52:07 -07:00
example_config_freepdk45.py
Fixed nominal_corner_only parameter.
2020-10-30 15:52:07 -07:00
example_config_scn4m_subm.py
Fixed nominal_corner_only parameter.
2020-10-30 15:52:07 -07:00
giant_config_scn4m_subm.py
Fixed nominal_corner_only parameter.
2020-10-30 15:52:07 -07:00
medium_config_scn4m_subm.py
Fixed nominal_corner_only parameter.
2020-10-30 15:52:07 -07:00
riscv-freepdk45-8kbyte.py
Fixed nominal_corner_only parameter.
2020-10-30 15:52:07 -07:00
riscv-scn4m_subm-1kbyte-1rw1r.py
Create single port memory config examples.
2020-11-03 14:42:56 -08:00
riscv-scn4m_subm-2kbyte-1rw1r.py
Create single port memory config examples.
2020-11-03 14:42:56 -08:00
riscv-scn4m_subm-4kbyte-1rw1r.py
Create single port memory config examples.
2020-11-03 14:42:56 -08:00
riscv-scn4m_subm-8kbyte-1rw1r.py
Create single port memory config examples.
2020-11-03 14:42:56 -08:00
riscv-scn4m_subm-16kbyte-1rw1r.py
Create single port memory config examples.
2020-11-03 14:42:56 -08:00
riscv-scn4m_subm-32kbyte.py
Fixed nominal_corner_only parameter.
2020-10-30 15:52:07 -07:00
riscv-sky130-1kbyte-1rw1r.py
Create single port memory config examples.
2020-11-03 14:42:56 -08:00
riscv-sky130-1kbyte-1rw.py
Create single port memory config examples.
2020-11-03 14:42:56 -08:00
riscv-sky130-2kbyte-1rw1r.py
Create single port memory config examples.
2020-11-03 14:42:56 -08:00
riscv-sky130-2kbyte-1rw.py
Create single port memory config examples.
2020-11-03 14:42:56 -08:00
riscv-sky130-4kbyte-1rw1r.py
Create single port memory config examples.
2020-11-03 14:42:56 -08:00
riscv-sky130-4kbyte-1rw.py
Create single port memory config examples.
2020-11-03 14:42:56 -08:00