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OpenRAM/compiler/base
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Gary Mejia 9a36cce7ae Fixed formatting on all files
2023-06-14 12:28:36 -07:00
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__init__.py
Verilog ROM model created for testing
2023-06-12 15:35:54 -07:00
channel_route.py
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contact.py
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delay_data.py
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design.py
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errors.py
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geometry.py
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hierarchy_design.py
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hierarchy_layout.py
rom base passing tests with top level routing
2023-03-30 11:30:50 -07:00
hierarchy_spice.py
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lef.py
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logical_effort.py
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pin_layout.py
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power_data.py
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rom_verilog.py
Fixed formatting on all files
2023-06-14 12:28:36 -07:00
route.py
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timing_graph.py
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utils.py
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vector3d.py
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vector.py
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verilog.py
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wire_path.py
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wire_spice_model.py
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wire.py
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