Joey Kunzler 001bf1b827 merge conflict - port data

2020-06-02 14:15:39 -07:00

..

bitcell_1rw_1r.py

bitcell: Remove hardcoded signal pins

2020-02-12 15:37:51 +01:00

bitcell_1w_1r.py

bitcell: Remove hardcoded signal pins

2020-02-12 15:37:51 +01:00

bitcell_base.py

Refactor bitcell to bitcell_base. Pep8 format bitcells.

2019-10-06 01:08:23 +00:00

bitcell.py

Thin-cell decoder changes.

2020-05-29 10:36:07 -07:00

col_cap_bitcell_1rw_1r.py

update for end caps

2020-05-27 20:03:11 -07:00

dummy_bitcell_1rw_1r.py

bitcell: Remove hardcoded signal pins

2020-02-12 15:37:51 +01:00

dummy_bitcell_1w_1r.py

bitcell: Remove hardcoded signal pins

2020-02-12 15:37:51 +01:00

dummy_bitcell.py

bitcell: Remove hardcoded signal pins

2020-02-12 15:37:51 +01:00

dummy_pbitcell.py

Add bbox for special DRC rule boundary

2019-12-05 23:14:25 +00:00

pbitcell.py

Changes to simplify metal preferred directions and pitches.

2020-05-10 11:32:45 -07:00

replica_bitcell_1rw_1r.py

bitcell: Remove hardcoded signal pins

2020-02-12 15:37:51 +01:00

replica_bitcell_1w_1r.py

bitcell: Remove hardcoded signal pins

2020-02-12 15:37:51 +01:00

replica_bitcell.py

bitcell: Remove hardcoded signal pins

2020-02-12 15:37:51 +01:00

replica_pbitcell.py

Add bbox for special DRC rule boundary

2019-12-05 23:14:25 +00:00

row_cap_bitcell_1rw_1r.py

update for end caps

2020-05-27 20:03:11 -07:00