mirror of https://github.com/VLSIDA/OpenRAM.git
146 lines
5.3 KiB
Python
146 lines
5.3 KiB
Python
# See LICENSE for licensing information.
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#
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#Copyright (c) 2016-2019 Regents of the University of California and The Board
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#of Regents for the Oklahoma Agricultural and Mechanical College
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#(acting for and on behalf of Oklahoma State University)
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#All rights reserved.
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#
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from math import log
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import design
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from tech import drc
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import debug
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from sram_factory import factory
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from vector import vector
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from globals import OPTS
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class write_driver_array(design.design):
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"""
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Array of tristate drivers to write to the bitlines through the column mux.
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Dynamically generated write driver array of all bitlines.
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"""
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def __init__(self, name, columns, word_size):
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design.design.__init__(self, name)
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debug.info(1, "Creating {0}".format(self.name))
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self.add_comment("columns: {0}".format(columns))
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self.add_comment("word_size {0}".format(word_size))
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self.columns = columns
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self.word_size = word_size
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self.words_per_row = int(columns / word_size)
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_write_array()
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def create_layout(self):
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if self.bitcell.width > self.driver.width:
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self.width = self.columns * self.bitcell.width
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else:
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self.width = self.columns * self.driver.width
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self.height = self.driver.height
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self.place_write_array()
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self.add_layout_pins()
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self.DRC_LVS()
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def add_pins(self):
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for i in range(self.word_size):
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self.add_pin("data_{0}".format(i))
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for i in range(self.word_size):
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self.add_pin("bl_{0}".format(i))
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self.add_pin("br_{0}".format(i))
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self.add_pin("en")
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self.add_pin("vdd")
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self.add_pin("gnd")
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def add_modules(self):
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self.driver = factory.create(module_type="write_driver")
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self.add_mod(self.driver)
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# This is just used for measurements,
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# so don't add the module
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self.bitcell = factory.create(module_type="bitcell")
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def create_write_array(self):
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self.driver_insts = {}
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for i in range(0,self.columns,self.words_per_row):
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name = "write_driver{}".format(i)
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index = int(i/self.words_per_row)
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self.driver_insts[index]=self.add_inst(name=name,
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mod=self.driver)
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self.connect_inst(["data_{0}".format(index),
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"bl_{0}".format(index),
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"br_{0}".format(index),
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"en", "vdd", "gnd"])
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def place_write_array(self):
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if self.bitcell.width > self.driver.width:
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driver_spacing = self.bitcell.width
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else:
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driver_spacing = self.driver.width
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for i in range(0,self.columns,self.words_per_row):
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index = int(i/self.words_per_row)
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base = vector(i * driver_spacing,0)
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self.driver_insts[index].place(base)
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def add_layout_pins(self):
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for i in range(self.word_size):
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din_pin = self.driver_insts[i].get_pin("din")
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self.add_layout_pin(text="data_{0}".format(i),
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layer="metal2",
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offset=din_pin.ll(),
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width=din_pin.width(),
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height=din_pin.height())
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bl_pin = self.driver_insts[i].get_pin("bl")
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self.add_layout_pin(text="bl_{0}".format(i),
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layer="metal2",
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offset=bl_pin.ll(),
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width=bl_pin.width(),
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height=bl_pin.height())
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br_pin = self.driver_insts[i].get_pin("br")
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self.add_layout_pin(text="br_{0}".format(i),
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layer="metal2",
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offset=br_pin.ll(),
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width=br_pin.width(),
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height=br_pin.height())
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for n in ["vdd", "gnd"]:
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pin_list = self.driver_insts[i].get_pins(n)
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for pin in pin_list:
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pin_pos = pin.center()
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# Add the M2->M3 stack
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=pin_pos)
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self.add_layout_pin_rect_center(text=n,
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layer="metal3",
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offset=pin_pos)
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self.add_layout_pin(text="en",
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layer="metal1",
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offset=self.driver_insts[0].get_pin("en").ll().scale(0,1),
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width=self.width,
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height=drc('minwidth_metal1'))
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def get_w_en_cin(self):
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"""Get the relative capacitance of all the enable connections in the bank"""
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#The enable is connected to a nand2 for every row.
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return self.driver.get_w_en_cin() * len(self.driver_insts)
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