mirror of https://github.com/VLSIDA/OpenRAM.git
145 lines
5.6 KiB
Python
145 lines
5.6 KiB
Python
#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California
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# All rights reserved.
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#
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from sram_factory import factory
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from .sky130_bitcell_base_array import sky130_bitcell_base_array
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from globals import OPTS
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class sky130_row_cap_array(sky130_bitcell_base_array):
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"""
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Generate a dummy row/column for the replica array.
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"""
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def __init__(self, rows, cols, column_offset=0, mirror=0, name=""):
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# Don't call the regular col-cap_array constructor since we don't want its constructor, just
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# some of it's useful member functions
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sky130_bitcell_base_array.__init__(self, rows=rows, cols=cols, column_offset=column_offset, name=name)
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self.rows = rows
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self.cols = cols
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self.column_offset = column_offset
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self.mirror = mirror
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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""" Create and connect the netlist """
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self.create_all_wordline_names()
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# This module has no bitlines
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# self.create_all_bitline_names()
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.place_array("dummy_r{0}_c{1}", self.mirror)
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self.add_layout_pins()
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self.width = max([x.rx() for x in self.insts])
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self.height = max([x.uy() for x in self.insts])
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self.add_boundary()
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self.DRC_LVS()
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def add_modules(self):
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""" Add the modules used in this design """
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if self.column_offset == 0:
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self.top_corner = factory.create(module_type="corner", location="ul")
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self.bottom_corner =factory.create(module_type="corner", location="ll")
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self.rowend1 = factory.create(module_type="row_cap", version="rowend_replica")
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self.rowend2 = factory.create(module_type="row_cap", version="rowenda_replica")
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else:
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self.top_corner = factory.create(module_type="corner", location="ur")
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self.bottom_corner = factory.create(module_type="corner", location="lr")
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self.rowend1 = factory.create(module_type="row_cap", version="rowend")
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self.rowend2 = factory.create(module_type="row_cap", version="rowenda")
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self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
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def create_instances(self):
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""" Create the module instances used in this design """
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self.cell_inst = {}
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self.array_layout = []
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alternate_bitcell = (self.rows + 1) % 2
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for row in range(self.rows + 2):
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row_layout = []
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name="rca_{0}".format(row)
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# Top/bottom cell are always dummy cells.
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# Regular array cells are replica cells (>left_rbl and <rows-right_rbl)
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# Replic bit specifies which other bit (in the full range (0,rows) to make a replica cell.
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if (row < self.rows + 1 and row > 0):
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if alternate_bitcell == 0:
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row_layout.append(self.rowend1)
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self.cell_inst[row]=self.add_inst(name=name, mod=self.rowend1)
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self.connect_inst(["wl_0_{}".format(row - 1), "vdd"])
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alternate_bitcell = 1
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else:
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row_layout.append(self.rowend2)
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self.cell_inst[row] = self.add_inst(name=name, mod=self.rowend2)
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self.connect_inst(["wl_0_{}".format(row - 1), "vdd"])
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alternate_bitcell = 0
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elif (row == 0):
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row_layout.append(self.bottom_corner)
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self.cell_inst[row]=self.add_inst(name=name, mod=self.bottom_corner)
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self.connect_inst(self.get_corner_pins())
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elif (row == self.rows + 1):
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row_layout.append(self.top_corner)
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self.cell_inst[row]=self.add_inst(name=name, mod=self.top_corner)
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self.connect_inst(self.get_corner_pins())
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self.array_layout.append(row_layout)
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def place_array(self, name_template, row_offset=0):
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xoffset = 0.0
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yoffset = 0.0
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for row in range(len(self.insts)):
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inst = self.insts[row]
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if row == 0:
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inst.place(offset=[xoffset, yoffset + inst.height], mirror="MX")
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elif row == len(self.insts)-1:
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inst.place(offset=[xoffset, yoffset])
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else:
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if row % 2 ==0:
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inst.place(offset=[xoffset, yoffset + inst.height], mirror="MX")
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else:
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inst.place(offset=[xoffset, yoffset])
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yoffset += inst.height
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def add_pins(self):
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for row in range(self.rows + 2):
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for port in self.all_ports:
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self.add_pin("wl_{}_{}".format(port, row), "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_layout_pins(self):
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""" Add the layout pins """
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for row in range(0, self.rows + 1):
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if row > 0 and row < self.rows + 1:
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wl_pin = self.cell_inst[row].get_pin("wl")
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self.add_layout_pin(text="wl_0_{0}".format(row -1),
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layer=wl_pin.layer,
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offset=wl_pin.ll().scale(0, 1),
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width=self.width,
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height=wl_pin.height())
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# Add vdd/gnd via stacks
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for row in range(1, self.rows):
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inst = self.cell_inst[row]
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for pin_name in ["vdd", "gnd"]:
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for pin in inst.get_pins(pin_name):
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self.copy_layout_pin(inst, pin_name)
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