mirror of https://github.com/VLSIDA/OpenRAM.git
196 lines
8.8 KiB
Python
196 lines
8.8 KiB
Python
#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California
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# All rights reserved.
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#
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from .sky130_bitcell_base_array import sky130_bitcell_base_array
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from sram_factory import factory
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from globals import OPTS
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from base import geometry
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from tech import layer
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class sky130_dummy_array(sky130_bitcell_base_array):
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"""
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Generate a dummy row/column for the replica array.
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"""
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def __init__(self, rows, cols, column_offset=0, row_offset=0 ,mirror=0, location="", name=""):
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super().__init__(rows=rows, cols=cols, column_offset=column_offset, name=name)
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self.mirror = mirror
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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""" Create and connect the netlist """
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# This will create a default set of bitline/wordline names
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self.create_all_bitline_names()
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self.create_all_wordline_names()
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.place_array("dummy_r{0}_c{1}", self.mirror)
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self.add_layout_pins()
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self.add_supply_pins()
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self.add_boundary()
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self.DRC_LVS()
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def add_modules(self):
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""" Add the modules used in this design """
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self.dummy_cell = factory.create(module_type=OPTS.dummy_bitcell, version="opt1")
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self.dummy_cell2 = factory.create(module_type=OPTS.dummy_bitcell, version="opt1a")
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self.strap = factory.create(module_type="internal", version="wlstrap")
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self.strap2 = factory.create(module_type="internal", version="wlstrap_p")
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self.strap3 = factory.create(module_type="internal", version="wlstrapa")
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self.strap4 = factory.create(module_type="internal", version="wlstrapa_p")
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self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
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def create_instances(self):
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""" Create the module instances used in this design """
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self.cell_inst = {}
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self.array_layout = []
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alternate_bitcell = (self.row_size + 1) % 2
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for row in range(0, self.row_size):
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row_layout = []
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alternate_strap = (self.row_size + 1) % 2
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for col in range(0, self.column_size):
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if alternate_bitcell == 1:
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row_layout.append(self.dummy_cell)
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self.cell_inst[row, col]=self.add_inst(name="row_{}_col_{}_bitcell".format(row, col),
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mod=self.dummy_cell)
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else:
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row_layout.append(self.dummy_cell2)
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self.cell_inst[row, col]=self.add_inst(name="row_{}_col_{}_bitcell".format(row, col),
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mod=self.dummy_cell2)
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self.connect_inst(self.get_bitcell_pins(row, col))
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if col != self.column_size - 1:
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if alternate_strap:
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if col % 2:
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name="row_{}_col_{}_wlstrap_p".format(row, col)
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row_layout.append(self.strap4)
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self.add_inst(name=name,
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mod=self.strap4)
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else:
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name="row_{}_col_{}_wlstrapa_p".format(row, col)
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row_layout.append(self.strap2)
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self.add_inst(name=name,
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mod=self.strap2)
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alternate_strap = 0
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else:
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if col % 2:
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name="row_{}_col_{}_wlstrap".format(row, col)
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row_layout.append(self.strap)
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self.add_inst(name=name,
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mod=self.strap)
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else:
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name="row_{}_col_{}_wlstrapa".format(row, col)
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row_layout.append(self.strap3)
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self.add_inst(name=name,
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mod=self.strap3)
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alternate_strap = 1
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self.connect_inst(self.get_strap_pins(row, col, name))
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if alternate_bitcell == 0:
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alternate_bitcell = 1
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else:
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alternate_bitcell = 0
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self.array_layout.append(row_layout)
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def add_pins(self):
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# bitline pins are not added because they are floating
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for bl in range(self.column_size):
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self.add_pin("bl_0_{}".format(bl))
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self.add_pin("br_0_{}".format(bl))
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for wl_name in self.get_wordline_names():
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self.add_pin(wl_name, "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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#self.add_pin("vpb", "BIAS")
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#Sself.add_pin("vnb", "BIAS")
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def add_layout_pins(self):
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""" Add the layout pins """
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bitline_names = self.cell.get_all_bitline_names()
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for col in range(self.column_size):
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for port in self.all_ports:
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bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port])
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text = "bl_{0}_{1}".format(port, col)
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self.add_layout_pin(text=text,
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layer=bl_pin.layer,
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offset=bl_pin.ll().scale(1, 0),
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width=bl_pin.width(),
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height=self.height)
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br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1])
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text = "br_{0}_{1}".format(port, col)
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self.add_layout_pin(text=text,
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layer=br_pin.layer,
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offset=br_pin.ll().scale(1, 0),
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width=br_pin.width(),
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height=self.height)
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# self.add_rect(layer=bl_pin.layer,
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# offset=bl_pin.ll().scale(1, 0),
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# width=bl_pin.width(),
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# height=self.height)
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# self.add_rect(layer=br_pin.layer,
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# offset=br_pin.ll().scale(1, 0),
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# width=br_pin.width(),
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# height=self.height)
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wl_names = self.cell.get_all_wl_names()
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for row in range(self.row_size):
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for port in self.all_ports:
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wl_pin = self.cell_inst[row, 0].get_pin(wl_names[port])
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self.add_layout_pin(text="wl_{0}_{1}".format(port, row),
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layer=wl_pin.layer,
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offset=wl_pin.ll().scale(0, 1),
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width=self.width,
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height=wl_pin.height())
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# Copy a vdd/gnd layout pin from every cell
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for row in range(self.row_size):
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for col in range(self.column_size):
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inst = self.cell_inst[row, col]
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for pin_name in ["vdd", "gnd"]:
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self.copy_layout_pin(inst, pin_name)
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def add_supply_pins(self):
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for row in range(self.row_size):
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for col in range(self.column_size):
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inst = self.cell_inst[row, col]
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if 'VPB' or 'vpb' in self.cell_inst[row, col].mod.pins:
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pin = inst.get_pin("vpb")
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self.objs.append(geometry.rectangle(layer["nwell"],
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pin.ll(),
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pin.width(),
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pin.height()))
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self.objs.append(geometry.label("vdd", layer["nwell"], pin.center()))
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if 'VNB' or 'vnb' in self.cell_inst[row, col].mod.pins:
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try:
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from tech import layer_override
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if layer_override['VNB']:
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pin = inst.get_pin("vnb")
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self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center()))
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self.objs.append(geometry.rectangle(layer["pwellp"],
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pin.ll(),
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pin.width(),
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pin.height()))
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except:
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pin = inst.get_pin("vnb")
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self.add_label("vdd", pin.layer, pin.center())
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def input_load(self):
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# FIXME: This appears to be old code from previous characterization. Needs to be updated.
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wl_wire = self.gen_wl_wire()
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return wl_wire.return_input_cap()
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