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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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1175f515c83eef5e7cfa3c181a7a11b24705c1cd
OpenRAM/compiler/verify
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Matt Guthaus 012c3923be Create empty setup.tcl file as workaround for resetting netgen LVS options until Tim fix's bug.
2018-01-31 08:28:53 -08:00
..
__init__.py
Only check if using magic with freepdk when LVSDRC is enabled.
2018-01-17 07:38:29 -08:00
assura.py
Improve global and code structure using modules.
2017-11-16 13:52:58 -08:00
calibre.py
Initial DRC with Magic is done.
2018-01-12 14:39:42 -08:00
magic.py
Create empty setup.tcl file as workaround for resetting netgen LVS options until Tim fix's bug.
2018-01-31 08:28:53 -08:00
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