mirror of
https://github.com/VLSIDA/OpenRAM.git
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ThVerg
1123f733bd
The sky130 magic techfile splits nfet extraction on device width: device msubcircuit sky130_fd_pr__nfet_01v8 nfet,scnfet ... w>=0.42 device msubcircuit sky130_fd_pr__special_nfet_01v8 scnfet ... w<0.42 ptx always emitted spice["nmos"], so every gate built from a minimum-width device (drc["minwidth_tx"] = 0.36) was netlisted as sky130_fd_pr__nfet_01v8 while magic extracted it as sky130_fd_pr__special_nfet_01v8. netgen then reported a device class mismatch in each such cell: Circuit 1: sky130_fd_pr__special_nfet_01v8 (1) | Circuit 2: (no matching element) Circuit 1: (no matching element) | Circuit 2: sky130_fd_pr__nfet_01v8 (1) The signed-off macros shipped in sky130A/libs.ref/sky130_sram_macros use special_nfet_01v8 at this geometry, so this restores the naming those were built with. ptx now asks the technology for a narrow-device model, keyed by width. Technologies that declare no such model are unaffected, and there is no equivalent split for pfets so only the nmos is declared. After this change pinv and pinv_dec report "Netlists match uniquely" where they previously mismatched. Verified with ngspice that special_nfet_01v8 resolves through sky130.lib.spice, so characterization is unaffected. Co-Authored-By: Claude Opus 5 (1M context) <[email protected]> Claude-Session: https://claude.ai/code/session_01FcKSuKSchDEd7MqT8AffpN
593 lines
25 KiB
Python
593 lines
25 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2024 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from openram import debug
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from openram.base import design
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from openram.base import logical_effort
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from openram.base import vector
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from openram.sram_factory import factory
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from openram.tech import layer, drc, spice
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from openram.tech import cell_properties as cell_props
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from openram import OPTS
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class ptx(design):
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"""
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This module generates gds and spice of a parametrically NMOS or
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PMOS sized transistor. Pins are accessed as D, G, S, B. Width is
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the transistor width. Mults is the number of transistors of the
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given width. Total width is therefore mults*width. Options allow
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you to connect the fingered gates and active for parallel devices.
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The add_*_contact option tells which layer to bring source/drain up to.
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ll, ur, width and height refer to the active area.
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Wells and poly may extend beyond this.
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"""
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def __init__(self,
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name="",
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width=drc("minwidth_tx"),
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mults=1,
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tx_type="nmos",
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add_source_contact=None,
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add_drain_contact=None,
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series_devices=False,
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connect_drain_active=False,
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connect_source_active=False,
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connect_poly=False,
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num_contacts=None,
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):
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if "li" in layer:
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self.route_layer = "li"
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else:
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self.route_layer = "m1"
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# Default contacts are the lowest layer
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if add_source_contact == None:
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add_source_contact = self.route_layer
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# Default contacts are the lowest layer
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if add_drain_contact == None:
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add_drain_contact = self.route_layer
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# We need to keep unique names because outputting to GDSII
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# will use the last record with a given name. I.e., you will
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# over-write a design in GDS if one has and the other doesn't
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# have poly connected, for example.
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name = "{0}_m{1}_w{2:.3f}".format(tx_type, mults, width)
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name += "_s{}".format(add_source_contact)
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name += "_d{}".format(add_drain_contact)
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if series_devices:
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name += "_sd"
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if connect_drain_active:
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name += "_da"
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if connect_source_active:
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name += "_sa"
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if connect_poly:
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name += "_p"
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if num_contacts:
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name += "_c{}".format(num_contacts)
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# replace periods with underscore for newer spice compatibility
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name = name.replace('.', '_')
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debug.info(3, "creating ptx {0}".format(name))
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super().__init__(name)
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self.tx_type = tx_type
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self.mults = mults
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self.tx_width = width
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self.connect_drain_active = connect_drain_active
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self.connect_source_active = connect_source_active
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self.connect_poly = connect_poly
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self.add_source_contact = add_source_contact
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self.add_drain_contact = add_drain_contact
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self.series_devices = series_devices
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self.num_contacts = num_contacts
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self.route_layer_width = drc("minwidth_{}".format(self.route_layer))
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self.route_layer_space = drc("{0}_to_{0}".format(self.route_layer))
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# Since it has variable height, it is not a pgate.
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self.create_netlist()
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# We must always create ptx layout for pbitcell
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# some transistor sizes in other netlist depend on pbitcell
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self.create_layout()
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ll = self.find_lowest_coords()
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ur = self.find_highest_coords()
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self.add_boundary(ll, ur)
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# (0,0) will be the corner of the active area (not the larger well)
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self.translate_all(self.active_offset)
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def create_layout(self):
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"""Calls all functions related to the generation of the layout"""
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self.setup_layout_constants()
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self.add_active()
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self.add_well_implant()
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self.add_poly()
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self.add_active_contacts()
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# for run-time, we won't check every transitor DRC independently
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# but this may be uncommented for debug purposes
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# self.DRC()
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def get_model_name(self):
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"""
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Return the device model name for this transistor's width.
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Some technologies model narrow devices with a separate model. In
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sky130, an nfet narrower than 0.42um is extracted as
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sky130_fd_pr__special_nfet_01v8 rather than sky130_fd_pr__nfet_01v8
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(see the "device msubcircuit" rules in sky130A.tech), so the netlist
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must use the same name or LVS reports a device class mismatch on
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every gate built from a minimum-width device.
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"""
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narrow_model = spice.get("{}_narrow".format(self.tx_type))
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narrow_width = spice.get("{}_narrow_max_width".format(self.tx_type))
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if narrow_model and narrow_width and self.tx_width < narrow_width:
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return narrow_model
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return spice[self.tx_type]
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def create_netlist(self):
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pin_list = ["D", "G", "S", "B"]
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if self.tx_type == "nmos":
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body_dir = "GROUND"
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else:
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body_dir = "POWER"
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self.model_name = self.get_model_name()
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dir_list = ["INOUT", "INPUT", "INOUT", body_dir]
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self.add_pin_list(pin_list, dir_list)
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# Just make a guess since these will actually
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# be decided in the layout later.
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area_sd = 2.5 * self.poly_width * self.tx_width
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perimeter_sd = 2 * self.poly_width + 2 * self.tx_width
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self.channel_length = drc("minlength_channel")
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if cell_props.ptx.model_is_subckt:
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# sky130
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main_str = "X{{0}} {{1}} {0} m={1} w={2} l={3} ".format(self.model_name,
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self.mults,
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self.tx_width,
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self.channel_length)
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# Perimeters are in microns
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# Area is in u since it is microns square
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area_str = "pd={0:.2f} ps={0:.2f} as={1:.2f}u ad={1:.2f}u".format(perimeter_sd,
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area_sd)
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else:
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main_str = "M{{0}} {{1}} {0} m={1} w={2}u l={3}u ".format(self.model_name,
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self.mults,
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self.tx_width,
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self.channel_length)
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area_str = "pd={0:.2f}u ps={0:.2f}u as={1:.2f}p ad={1:.2f}p".format(perimeter_sd,
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area_sd)
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self.spice_device = main_str + area_str
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self.spice.append("\n* spice ptx " + self.spice_device)
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if cell_props.ptx.model_is_subckt and OPTS.lvs_exe and OPTS.lvs_exe[0] == "calibre":
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# sky130 requires mult parameter too. It is not the same as m, but I don't understand it.
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# self.lvs_device = "X{{0}} {{1}} {0} m={1} w={2} l={3} mult=1".format(spice[self.tx_type],
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# self.mults,
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# self.tx_width,
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# drc("minwidth_poly"))
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# TEMP FIX: Use old device names if using Calibre.
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self.lvs_device = "M{{0}} {{1}} {0} m={1} w={2} l={3} mult=1".format("nshort" if self.tx_type == "nmos" else "pshort",
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self.mults,
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self.tx_width,
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self.channel_length)
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elif cell_props.ptx.model_is_subckt:
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self.lvs_device = "X{{0}} {{1}} {0} m={1} w={2}u l={3}u".format(self.model_name,
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self.mults,
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self.tx_width,
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self.channel_length)
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else:
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self.lvs_device = "M{{0}} {{1}} {0} m={1} w={2}u l={3}u ".format(self.model_name,
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self.mults,
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self.tx_width,
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self.channel_length)
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def setup_layout_constants(self):
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"""
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Pre-compute some handy layout parameters.
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"""
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if not self.num_contacts:
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self.num_contacts = self.calculate_num_contacts()
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# Determine layer types needed
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if self.tx_type == "nmos":
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self.implant_type = "n"
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self.well_type = "p"
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elif self.tx_type == "pmos":
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self.implant_type = "p"
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self.well_type = "n"
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else:
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self.error("Invalid transitor type.", -1)
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# This is not actually instantiated but used for calculations
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self.active_contact = factory.create(module_type="contact",
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layer_stack=self.active_stack,
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directions=("V", "V"),
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dimensions=(1, self.num_contacts))
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# This is the extra poly spacing due to the poly contact to poly contact pitch
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# of contacted gates
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extra_poly_contact_width = self.poly_contact.width - self.poly_width
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# This is the spacing between S/D contacts
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# This is the spacing between the poly gates
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self.min_poly_pitch = self.poly_space + self.poly_width
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self.contacted_poly_pitch = self.poly_space + self.poly_contact.width
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self.contact_pitch = 2 * self.active_contact_to_gate + self.poly_width + self.contact_width
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self.poly_pitch = max(self.min_poly_pitch,
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self.contacted_poly_pitch,
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self.contact_pitch)
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self.end_to_contact = 0.5 * self.active_contact.width
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# Active width is determined by enclosure on both ends and contacted pitch,
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# at least one poly and n-1 poly pitches
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self.active_width = 2 * self.end_to_contact + self.active_contact.width \
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+ 2 * self.active_contact_to_gate + self.poly_width + (self.mults - 1) * self.poly_pitch
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# Active height is either the transistor width or the wide enough to enclose the active contact
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self.active_height = self.tx_width
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# Poly height must include poly extension over active
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self.poly_height = self.active_height + 2 * self.poly_extend_active
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self.active_offset = vector([self.well_enclose_active] * 2)
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# Well enclosure of active, ensure minwidth as well
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well_name = "{}well".format(self.well_type)
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if well_name in layer:
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well_width_rule = drc("minwidth_" + well_name)
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self.well_width = max(self.active_width + 2 * self.well_enclose_active,
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well_width_rule)
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self.well_height = max(self.active_height + 2 * self.well_enclose_active,
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well_width_rule)
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else:
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self.well_height = self.height
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self.well_width = self.width
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# We are going to shift the 0,0, so include that in the width and height
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self.height = self.active_height
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self.width = self.active_width
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# This is the center of the first active contact offset (centered vertically)
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self.contact_offset = self.active_offset + vector(0.5 * self.active_contact.width,
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0.5 * self.active_height)
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# Min area results are just flagged for now.
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debug.check(self.active_width * self.active_height >= self.minarea_active,
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"Minimum active area violated.")
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# We do not want to increase the poly dimensions to fix
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# an area problem as it would cause an LVS issue.
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debug.check(self.poly_width * self.poly_height >= self.minarea_poly,
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"Minimum poly area violated.")
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def connect_fingered_poly(self, poly_positions):
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"""
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Connect together the poly gates and create the single gate pin.
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The poly positions are the center of the poly gates
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and we will add a single horizontal connection.
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"""
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# Nothing to do if there's one poly gate
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if len(poly_positions)<2:
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return
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# The width of the poly is from the left-most to right-most poly gate
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poly_width = poly_positions[-1].x - poly_positions[0].x + self.poly_width
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if self.tx_type == "pmos":
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# This can be limited by poly to active spacing
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# or the poly extension
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distance_below_active = self.poly_width + max(self.poly_to_active,
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0.5 * self.poly_height)
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poly_offset = poly_positions[0] - vector(0.5 * self.poly_width,
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distance_below_active)
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else:
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# This can be limited by poly to active spacing
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# or the poly extension
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distance_above_active = max(self.poly_to_active,
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0.5 * self.poly_height)
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poly_offset = poly_positions[0] + vector(-0.5 * self.poly_width,
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distance_above_active)
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# Remove the old pin and add the new one
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# only keep the main pin
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self.remove_layout_pin("G")
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self.add_layout_pin(text="G",
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layer="poly",
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offset=poly_offset,
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width=poly_width,
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height=self.poly_width)
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def connect_fingered_active(self, positions, pin_name, top):
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"""
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Connect each contact up/down to a source or drain pin
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"""
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if len(positions) <= 1:
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return
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layer_space = getattr(self, "{}_space".format(self.route_layer))
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layer_width = getattr(self, "{}_width".format(self.route_layer))
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# This is the distance that we must route up or down from the center
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# of the contacts to avoid DRC violations to the other contacts
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pin_offset = vector(0,
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0.5 * self.active_contact.second_layer_height + layer_space + 0.5 * layer_width)
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# This is the width of a m1 extend the ends of the pin
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end_offset = vector(layer_width / 2.0, 0)
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# We move the opposite direction from the bottom
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if not top:
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offset = pin_offset.scale(-1, -1)
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else:
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offset = pin_offset
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# remove the individual connections
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self.remove_layout_pin(pin_name)
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# Add each vertical segment
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for a in positions:
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self.add_path(self.route_layer,
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[a, a + offset])
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# Add a single horizontal pin
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self.add_layout_pin_segment_center(text=pin_name,
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layer=self.route_layer,
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start=positions[0] + offset - end_offset,
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end=positions[-1] + offset + end_offset)
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def add_poly(self):
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"""
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Add the poly gates(s) and (optionally) connect them.
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"""
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# poly is one contacted spacing from the end and down an extension
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poly_offset = self.contact_offset \
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+ vector(0.5 * self.active_contact.width + 0.5 * self.poly_width + self.active_contact_to_gate, 0)
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# poly_positions are the bottom center of the poly gates
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self.poly_positions = []
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self.poly_gates = []
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# It is important that these are from left to right,
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# so that the pins are in the right
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# order for the accessors
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for i in range(0, self.mults):
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# Add this duplicate rectangle in case we remove
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# the pin when joining fingers
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self.add_rect_center(layer="poly",
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offset=poly_offset,
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height=self.poly_height,
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width=self.poly_width)
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gate = self.add_layout_pin_rect_center(text="G",
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layer="poly",
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offset=poly_offset,
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height=self.poly_height,
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width=self.poly_width)
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self.poly_positions.append(poly_offset)
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self.poly_gates.append(gate)
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poly_offset = poly_offset + vector(self.poly_pitch, 0)
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if self.connect_poly:
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self.connect_fingered_poly(self.poly_positions)
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def add_active(self):
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"""
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Adding the diffusion (active region = diffusion region)
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"""
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self.active = self.add_rect(layer="active",
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offset=self.active_offset,
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width=self.active_width,
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height=self.active_height)
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# If the implant must enclose the active, shift offset
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# and increase width/height
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enclose_width = self.implant_enclose_active
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enclose_offset = [enclose_width] * 2
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self.implant = self.add_rect(layer="{}implant".format(self.implant_type),
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offset=self.active_offset - enclose_offset,
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width=self.active_width + 2 * enclose_width,
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height=self.active_height + 2 * enclose_width)
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def add_well_implant(self):
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"""
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Add an (optional) well and implant for the type of transistor.
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"""
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well_name = "{}well".format(self.well_type)
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if not (well_name in layer or "vtg" in layer):
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return
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center_pos = self.active_offset + vector(0.5 * self.active_width,
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0.5 * self.active_height)
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well_ll = center_pos - vector(0.5 * self.well_width,
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0.5 * self.well_height)
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if well_name in layer:
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well = self.add_rect(layer=well_name,
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offset=well_ll,
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width=self.well_width,
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height=self.well_height)
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setattr(self, well_name, well)
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if "vtg" in layer:
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self.add_rect(layer="vtg",
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offset=well_ll,
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width=self.well_width,
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height=self.well_height)
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def calculate_num_contacts(self):
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"""
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Calculates the possible number of source/drain contacts in a finger.
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For now, it is hard set as 1.
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"""
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return 1
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def add_active_contacts(self):
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"""
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Add the active contacts to the transistor.
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"""
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drain_positions = []
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source_positions = []
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# Keep a list of the source/drain contacts
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self.source_contacts = []
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self.drain_contacts = []
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|
|
|
# First one is always a SOURCE
|
|
label = "S"
|
|
pos = self.contact_offset
|
|
if self.add_source_contact:
|
|
contact = self.add_diff_contact(label, pos)
|
|
self.source_contacts.append(contact)
|
|
else:
|
|
self.add_layout_pin_rect_center(text=label,
|
|
layer="active",
|
|
offset=pos)
|
|
source_positions.append(pos)
|
|
|
|
# Skip these if they are going to be in series
|
|
if not self.series_devices:
|
|
for (poly1, poly2) in zip(self.poly_positions, self.poly_positions[1:]):
|
|
pos = vector(0.5 * (poly1.x + poly2.x),
|
|
self.contact_offset.y)
|
|
# Alternate source and drains
|
|
if label == "S":
|
|
label = "D"
|
|
drain_positions.append(pos)
|
|
else:
|
|
label = "S"
|
|
source_positions.append(pos)
|
|
|
|
if (label=="S" and self.add_source_contact):
|
|
contact = self.add_diff_contact(label, pos)
|
|
self.source_contacts.append(contact)
|
|
elif (label=="D" and self.add_drain_contact):
|
|
contact = self.add_diff_contact(label, pos)
|
|
self.drain_contacts.append(contact)
|
|
else:
|
|
self.add_layout_pin_rect_center(text=label,
|
|
layer="active",
|
|
offset=pos)
|
|
|
|
pos = vector(self.active_offset.x + self.active_width - 0.5 * self.active_contact.width,
|
|
self.contact_offset.y)
|
|
# Last one is the opposite of previous
|
|
if label == "S":
|
|
label = "D"
|
|
drain_positions.append(pos)
|
|
else:
|
|
label = "S"
|
|
source_positions.append(pos)
|
|
|
|
if (label=="S" and self.add_source_contact):
|
|
contact = self.add_diff_contact(label, pos)
|
|
self.source_contacts.append(contact)
|
|
elif (label=="D" and self.add_drain_contact):
|
|
contact = self.add_diff_contact(label, pos)
|
|
self.drain_contacts.append(contact)
|
|
else:
|
|
self.add_layout_pin_rect_center(text=label,
|
|
layer="active",
|
|
offset=pos)
|
|
|
|
if self.connect_source_active:
|
|
self.connect_fingered_active(source_positions, "S", top=(self.tx_type=="pmos"))
|
|
|
|
if self.connect_drain_active:
|
|
self.connect_fingered_active(drain_positions, "D", top=(self.tx_type=="nmos"))
|
|
|
|
def get_stage_effort(self, cout):
|
|
"""Returns an object representing the parameters for delay in tau units."""
|
|
|
|
# FIXME: Using the same definition as the pinv.py.
|
|
parasitic_delay = 1
|
|
size = self.mults * self.tx_width / drc("minwidth_tx")
|
|
return logical_effort(self.name,
|
|
size,
|
|
self.input_load(),
|
|
cout,
|
|
parasitic_delay)
|
|
|
|
def input_load(self):
|
|
"""
|
|
Returns the relative gate cin of the tx
|
|
"""
|
|
|
|
# FIXME: this will be applied for the loads of the drain/source
|
|
return self.mults * self.tx_width / drc("minwidth_tx")
|
|
|
|
def add_diff_contact(self, label, pos):
|
|
|
|
if label == "S":
|
|
layer = self.add_source_contact
|
|
elif label == "D":
|
|
layer = self.add_drain_contact
|
|
else:
|
|
debug.error("Invalid source drain name.")
|
|
|
|
if layer != "active":
|
|
via=self.add_via_stack_center(offset=pos,
|
|
from_layer="active",
|
|
to_layer=layer,
|
|
size=(1, self.num_contacts),
|
|
directions=("V", "V"),
|
|
implant_type=self.implant_type,
|
|
well_type=self.well_type)
|
|
|
|
pin_height = via.mod.second_layer_height
|
|
pin_width = via.mod.second_layer_width
|
|
else:
|
|
via = None
|
|
|
|
pin_height = None
|
|
pin_width = None
|
|
|
|
# Source drain vias are all vertical
|
|
self.add_layout_pin_rect_center(text=label,
|
|
layer=layer,
|
|
offset=pos,
|
|
width=pin_width,
|
|
height=pin_height)
|
|
|
|
return(via)
|
|
|
|
def get_cin(self):
|
|
"""Returns the relative gate cin of the tx"""
|
|
return self.tx_width / drc("minwidth_tx")
|
|
|
|
def build_graph(self, graph, inst_name, port_nets):
|
|
"""
|
|
Adds edges based on inputs/outputs.
|
|
Overrides base class function.
|
|
"""
|
|
self.add_graph_edges(graph, port_nets)
|
|
|
|
def is_non_inverting(self):
|
|
"""Return input to output polarity for module"""
|
|
|
|
return True
|
|
|
|
def get_on_resistance(self):
|
|
"""On resistance of pinv, defined by single nmos"""
|
|
is_nchannel = (self.tx_type == "nmos")
|
|
stack = 1
|
|
is_cell = False
|
|
return self.tr_r_on(self.tx_width, is_nchannel, stack, is_cell)
|
|
|
|
def get_input_capacitance(self):
|
|
"""Input cap of input, passes width of gates to gate cap function"""
|
|
return self.gate_c(self.tx_width)
|
|
|
|
def get_intrinsic_capacitance(self):
|
|
"""Get the drain capacitances of the TXs in the gate."""
|
|
return self.drain_c_(self.tx_width*self.mults,
|
|
1,
|
|
self.mults)
|