mirror of https://github.com/VLSIDA/OpenRAM.git
87 lines
5.8 KiB
Plaintext
87 lines
5.8 KiB
Plaintext
[globals/init_openram]: Initializing OpenRAM...
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[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_16936_temp/
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[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_8b_1024w_1bank_freepdk45.py
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[globals/read_config]: Output saved in ./
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[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
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|==============================================================================|
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|========= OpenRAM Compiler =========|
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|========= =========|
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|========= VLSI Design and Automation Lab =========|
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|========= University of California Santa Cruz CE Department =========|
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|========= =========|
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|========= VLSI Computer Architecture Research Group =========|
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|========= Oklahoma State University ECE Department =========|
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|========= =========|
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|========= Usage help: openram-user-group@ucsc.edu =========|
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|========= Development help: openram-dev-group@ucsc.edu =========|
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|========= Temp dir: /tmp/openram_mrg_16936_temp/ =========|
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|==============================================================================|
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Output files are sram_1rw_8b_1024w_4bank_freepdk45.(sp|gds|v|lib|lef)
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Technology: freepdk45
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Word size: 8
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Words: 1024
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Banks: 4
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[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
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[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
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[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
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** Start: 2018-02-24 22:05:07.033164 seconds
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[sram/compute_sizes]: Words per row: 4
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[control_logic/__init__]: Creating control_logic
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[ms_flop_array/__init__]: Creating msf_control
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[verify.calibre/run_drc]: msf_control Geometries: 1768 Checks: 167 Errors: 0
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[bitcell_array/__init__]: Creating bitline_load 13 x 1
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[verify.calibre/run_drc]: bitline_load Geometries: 3983 Checks: 167 Errors: 0
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[verify.calibre/run_drc]: delay_chain Geometries: 906 Checks: 167 Errors: 0
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[verify.calibre/run_drc]: replica_bitline Geometries: 5321 Checks: 167 Errors: 0
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[verify.calibre/run_drc]: control_logic Geometries: 8875 Checks: 167 Errors: 0
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[bitcell_array/__init__]: Creating bitcell_array 64 x 32
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[verify.calibre/run_drc]: bitcell_array Geometries: 622818 Checks: 167 Errors: 0
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[precharge_array/__init__]: Creating precharge_array
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[verify.calibre/run_drc]: precharge Geometries: 86 Checks: 167 Errors: 0
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[verify.calibre/run_drc]: precharge_array Geometries: 5570 Checks: 167 Errors: 0
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[single_level_column_mux_array/__init__]: Creating columnmux_array
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[verify.calibre/run_drc]: columnmux_array Geometries: 3029 Checks: 167 Errors: 0
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[sense_amp_array/__init__]: Creating sense_amp_array
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[verify.calibre/run_drc]: sense_amp_array Geometries: 1987 Checks: 167 Errors: 0
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[write_driver_array/__init__]: Creating write_driver_array
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[verify.calibre/run_drc]: write_driver_array Geometries: 2595 Checks: 167 Errors: 0
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[verify.calibre/run_drc]: pre2x4 Geometries: 969 Checks: 167 Errors: 0
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[verify.calibre/run_drc]: pre3x8 Geometries: 2251 Checks: 167 Errors: 0
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[verify.calibre/run_drc]: hierarchical_decoder_64rows Geometries: 34473 Checks: 167 Errors: 0
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[ms_flop_array/__init__]: Creating msf_address
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[verify.calibre/run_drc]: msf_address Geometries: 4703 Checks: 167 Errors: 0
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[ms_flop_array/__init__]: Creating msf_data_in
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[verify.calibre/run_drc]: msf_data_in Geometries: 4710 Checks: 167 Errors: 0
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[tri_gate_array/__init__]: Creating tri_gate_array
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[verify.calibre/run_drc]: tri_gate_array Geometries: 1428 Checks: 167 Errors: 0
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[verify.calibre/run_drc]: wordline_driver Geometries: 17538 Checks: 167 Errors: 0
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[verify.calibre/run_drc]: bank Geometries: 713631 Checks: 167 Errors: 0
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[ms_flop_array/__init__]: Creating msb_address
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[verify.calibre/run_drc]: msb_address Geometries: 1181 Checks: 167 Errors: 0
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[verify.calibre/run_drc]: sram_1rw_8b_1024w_4bank_freepdk45 Geometries: 3116996 Checks: 167 Errors: 0
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** SRAM creation: 155.1 seconds
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SP: Writing to ./sram_1rw_8b_1024w_4bank_freepdk45.sp
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** Spice writing: 0.0 seconds
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[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
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LIB: Characterizing...
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Performing simulation-based characterization with xa
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Trimming netlist to speed up characterization.
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[characterizer.lib/prepare_tables]: Loads: [ 0.052275 0.2091 1.6728 ]
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[characterizer.lib/prepare_tables]: Slews: [ 0.00125 0.005 0.04 ]
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[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
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[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_8b_1024w_4bank_freepdk45_TT_1p0V_25C.lib
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[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_16936_temp/reduced.sp.
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[characterizer.trim_spice/trim]: Keeping 1111111111 address
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[characterizer.trim_spice/trim]: Keeping 7 data bit
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[characterizer.trim_spice/trim]: Keeping bl[31] (trimming other BLs)
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[characterizer.trim_spice/trim]: Keeping wl[255] (trimming other WLs)
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[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
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[characterizer.delay/find_feasible_period]: Trying feasible period: 10.0ns
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[characterizer.delay/find_feasible_period]: Trying feasible period: 20.0ns
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[characterizer.delay/find_feasible_period]: Trying feasible period: 40.0ns
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[characterizer.delay/find_feasible_period]: Trying feasible period: 80.0ns
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[characterizer.delay/find_feasible_period]: Trying feasible period: 160.0ns
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[characterizer.delay/find_feasible_period]: Trying feasible period: 320.0ns
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[characterizer.delay/find_feasible_period]: Trying feasible period: 640.0ns
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ERROR: file delay.py: line 309: Timed out, could not find a feasible period.
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