mirror of https://github.com/VLSIDA/OpenRAM.git
63 lines
4.2 KiB
Plaintext
63 lines
4.2 KiB
Plaintext
[globals/init_openram]: Initializing OpenRAM...
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[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_3114_temp/
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[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_64b_1024w_2bank_freepdk45.py
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[globals/read_config]: Output saved in ./
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[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
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|==============================================================================|
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|========= OpenRAM Compiler =========|
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|========= =========|
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|========= VLSI Design and Automation Lab =========|
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|========= University of California Santa Cruz CE Department =========|
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|========= =========|
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|========= VLSI Computer Architecture Research Group =========|
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|========= Oklahoma State University ECE Department =========|
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|========= =========|
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|========= Usage help: openram-user-group@ucsc.edu =========|
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|========= Development help: openram-dev-group@ucsc.edu =========|
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|========= Temp dir: /tmp/openram_mrg_3114_temp/ =========|
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|==============================================================================|
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Output files are sram_1rw_64b_1024w_2bank_freepdk45.(sp|gds|v|lib|lef)
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Technology: freepdk45
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Word size: 64
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Words: 1024
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Banks: 2
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[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
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[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
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[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
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** Start: 2018-02-23 19:10:19.014431 seconds
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[sram/compute_sizes]: Words per row: 4
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[control_logic/__init__]: Creating control_logic
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[ms_flop_array/__init__]: Creating msf_control
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[verify.calibre/run_drc]: msf_control Geometries: 1768 Checks: 167 Errors: 0
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[bitcell_array/__init__]: Creating bitline_load 26 x 1
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[verify.calibre/run_drc]: bitline_load Geometries: 7961 Checks: 167 Errors: 0
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[verify.calibre/run_drc]: delay_chain Geometries: 906 Checks: 167 Errors: 0
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[verify.calibre/run_drc]: replica_bitline Geometries: 9383 Checks: 167 Errors: 0
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[verify.calibre/run_drc]: control_logic Geometries: 12956 Checks: 167 Errors: 0
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[bitcell_array/__init__]: Creating bitcell_array 128 x 256
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[verify.calibre/run_drc]: bitcell_array Geometries: 9962498 Checks: 167 Errors: 0
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[precharge_array/__init__]: Creating precharge_array
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[verify.calibre/run_drc]: precharge Geometries: 86 Checks: 167 Errors: 0
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[verify.calibre/run_drc]: precharge_array Geometries: 44546 Checks: 167 Errors: 0
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[single_level_column_mux_array/__init__]: Creating columnmux_array
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[verify.calibre/run_drc]: columnmux_array Geometries: 24197 Checks: 167 Errors: 0
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[sense_amp_array/__init__]: Creating sense_amp_array
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[verify.calibre/run_drc]: sense_amp_array Geometries: 15875 Checks: 167 Errors: 0
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[write_driver_array/__init__]: Creating write_driver_array
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[verify.calibre/run_drc]: write_driver_array Geometries: 20739 Checks: 167 Errors: 0
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[verify.calibre/run_drc]: pre2x4 Geometries: 969 Checks: 167 Errors: 0
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[verify.calibre/run_drc]: pre3x8 Geometries: 2251 Checks: 167 Errors: 0
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[verify.calibre/run_drc]: hierarchical_decoder_128rows Geometries: 65237 Checks: 167 Errors: 0
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[ms_flop_array/__init__]: Creating msf_address
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[verify.calibre/run_drc]: msf_address Geometries: 5290 Checks: 167 Errors: 0
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[ms_flop_array/__init__]: Creating msf_data_in
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[verify.calibre/run_drc]: msf_data_in Geometries: 37638 Checks: 167 Errors: 0
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[tri_gate_array/__init__]: Creating tri_gate_array
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[verify.calibre/run_drc]: tri_gate_array Geometries: 11396 Checks: 167 Errors: 0
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[verify.calibre/run_drc]: wordline_driver Geometries: 35074 Checks: 167 Errors: 0
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[verify.calibre/run_drc]: bank Geometries: 10255431 Checks: 167 Errors: 0
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[ms_flop_array/__init__]: Creating msb_address
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[verify.calibre/run_drc]: msb_address Geometries: 594 Checks: 167 Errors: 0
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ERROR: file calibre.py: line 131: sram_1rw_64b_1024w_2bank_freepdk45 Geometries: 20550242 Checks: 167 Errors: 1
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ERROR: file design.py: line 87: DRC failed for sram_1rw_64b_1024w_2bank_freepdk45
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