Michael Timothy Grimes 27427d4192 Bank level layout now works with pbitcell and 1RW. Column mux and array have been altered to accomodate multiport. Multiport changes to wordline driver were removed because they were unnecessary.		2018-09-09 22:06:29 -07:00
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pbitcell.py	Merging latest changes from multiport with changes made to pbitcell. Changing select code from other modules and tests to reflect changes made to pbitcell.	2018-09-06 19:36:50 -07:00
pgate.py	Make bitcell width/height not static. Update modules to use it for pbitcell.	2018-09-04 11:55:22 -07:00
pinv.py	Found rotate bug in transformCoordinate. Cleaned up transFlags.	2018-09-04 16:35:40 -07:00
pinvbuf.py	Make bitcell width/height not static. Update modules to use it for pbitcell.	2018-09-04 11:55:22 -07:00
pnand2.py	Make bitcell width/height not static. Update modules to use it for pbitcell.	2018-09-04 11:55:22 -07:00
pnand3.py	Make bitcell width/height not static. Update modules to use it for pbitcell.	2018-09-04 11:55:22 -07:00
pnor2.py	Make bitcell width/height not static. Update modules to use it for pbitcell.	2018-09-04 11:55:22 -07:00
precharge.py	Move place function to instance class rather than hierarchy.	2018-08-27 17:25:39 -07:00
ptx.py	Converted all modules to not run create_layout when netlist_only	2018-08-27 16:42:48 -07:00
single_level_column_mux.py	Bank level layout now works with pbitcell and 1RW. Column mux and array have been altered to accomodate multiport. Multiport changes to wordline driver were removed because they were unnecessary.	2018-09-09 22:06:29 -07:00