mirror of https://github.com/VLSIDA/OpenRAM.git
99 lines
3.7 KiB
Python
Executable File
99 lines
3.7 KiB
Python
Executable File
#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import unittest
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from testutils import *
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import sys,os
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sys.path.append(os.getenv("OPENRAM_HOME"))
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import globals
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from globals import OPTS
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import debug
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class path_test(openram_test):
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def runTest(self):
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config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
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globals.init_openram(config_file)
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import wire_path
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import tech
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import design
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min_space = 2 * tech.drc["minwidth_metal1"]
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layer_stack = ("metal1")
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# checks if we can retrace a path
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position_list = [[0,0],
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[0, 3 * min_space ],
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[4 * min_space, 3 * min_space ],
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[4 * min_space, 3 * min_space ],
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[0, 3 * min_space ],
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[0, 6 * min_space ]]
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w = design.design("path_test0")
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wire_path.wire_path(w,layer_stack, position_list)
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self.local_drc_check(w)
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min_space = 2 * tech.drc["minwidth_metal1"]
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layer_stack = ("metal1")
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old_position_list = [[0, 0],
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[0, 3 * min_space],
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[1 * min_space, 3 * min_space],
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[4 * min_space, 3 * min_space],
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[4 * min_space, 0],
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[7 * min_space, 0],
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[7 * min_space, 4 * min_space],
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[-1 * min_space, 4 * min_space],
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[-1 * min_space, 0]]
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position_list = [[x+min_space, y+min_space] for x,y in old_position_list]
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w = design.design("path_test1")
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wire_path.wire_path(w,layer_stack, position_list)
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self.local_drc_check(w)
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min_space = 2 * tech.drc["minwidth_metal2"]
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layer_stack = ("metal2")
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old_position_list = [[0, 0],
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[0, 3 * min_space],
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[1 * min_space, 3 * min_space],
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[4 * min_space, 3 * min_space],
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[4 * min_space, 0],
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[7 * min_space, 0],
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[7 * min_space, 4 * min_space],
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[-1 * min_space, 4 * min_space],
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[-1 * min_space, 0]]
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position_list = [[x-min_space, y-min_space] for x,y in old_position_list]
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w = design.design("path_test2")
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wire_path.wire_path(w, layer_stack, position_list)
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self.local_drc_check(w)
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min_space = 2 * tech.drc["minwidth_metal3"]
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layer_stack = ("metal3")
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position_list = [[0, 0],
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[0, 3 * min_space],
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[1 * min_space, 3 * min_space],
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[4 * min_space, 3 * min_space],
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[4 * min_space, 0],
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[7 * min_space, 0],
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[7 * min_space, 4 * min_space],
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[-1 * min_space, 4 * min_space],
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[-1 * min_space, 0]]
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# run on the reverse list
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position_list.reverse()
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w = design.design("path_test3")
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wire_path.wire_path(w, layer_stack, position_list)
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self.local_drc_check(w)
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globals.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main(testRunner=debugTestRunner())
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