mirror of https://github.com/VLSIDA/OpenRAM.git
131 lines
5.4 KiB
Python
131 lines
5.4 KiB
Python
import sys,re,shutil
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import debug
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import tech
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import math
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from .stimuli import *
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from .trim_spice import *
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from .charutils import *
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import utils
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from globals import OPTS
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from .delay import delay
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class bitline_delay(delay):
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"""Functions to test for the worst case delay in a target SRAM
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The current worst case determines a feasible period for the SRAM then tests
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several bits and record the delay and differences between the bits.
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"""
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def __init__(self, sram, spfile, corner):
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delay.__init__(self,sram,spfile,corner)
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self.period = tech.spice["feasible_period"]
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self.is_bitline_measure = True
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def create_measurement_names(self):
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"""Create measurement names. The names themselves currently define the type of measurement"""
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#Altering the names will crash the characterizer. TODO: object orientated approach to the measurements.
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self.bitline_meas_names = ["bl_volt", "br_volt"]
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def write_delay_measures(self):
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"""
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Write the measure statements to quantify the bitline voltage at sense amp enable 50%.
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"""
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self.sf.write("\n* Measure statements for delay and power\n")
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# Output some comments to aid where cycles start and
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for comment in self.cycle_comments:
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self.sf.write("* {}\n".format(comment))
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for read_port in self.targ_read_ports:
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self.write_bitline_measures_read_port(read_port)
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def write_bitline_measures_read_port(self, port):
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"""
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Write the measure statements to quantify the delay and power results for a read port.
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"""
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# add measure statements for delays/slews
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measure_bit = 0
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self.stim.gen_meas_find_voltage("bl_volt", "Xsram.s_en0", "Xsram.Xbank0.bl_{}".format(measure_bit), .5, "RISE", 3*self.period)
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self.stim.gen_meas_find_voltage("br_volt", "Xsram.s_en0", "Xsram.Xbank0.br_{}".format(measure_bit), .5, "RISE", 3*self.period)
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def gen_test_cycles_one_port(self, read_port, write_port):
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"""Sets a list of key time-points [ns] of the waveform (each rising edge)
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of the cycles to do a timing evaluation of a single port """
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# Create the inverse address for a scratch address
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inverse_address = self.calculate_inverse_address()
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# For now, ignore data patterns and write ones or zeros
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data_ones = "1"*self.word_size
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data_zeros = "0"*self.word_size
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if self.t_current == 0:
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self.add_noop_all_ports("Idle cycle (no positive clock edge)",
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inverse_address, data_zeros)
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self.add_write("W data 1 address {}".format(inverse_address),
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inverse_address,data_ones,write_port)
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self.add_write("W data 0 address {} to write value".format(self.probe_address),
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self.probe_address,data_zeros,write_port)
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self.measure_cycles[write_port]["write0"] = len(self.cycle_times)-1
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# This also ensures we will have a H->L transition on the next read
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self.add_read("R data 1 address {} to set DOUT caps".format(inverse_address),
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inverse_address,data_zeros,read_port)
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self.add_read("R data 0 address {} to check W0 worked".format(self.probe_address),
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self.probe_address,data_zeros,read_port)
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def run_delay_simulation(self):
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"""
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This tries to simulate a period and checks if the result works. If
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so, it returns True and the delays, slews, and powers. It
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works on the trimmed netlist by default, so powers do not
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include leakage of all cells.
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"""
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#Sanity Check
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debug.check(self.period > 0, "Target simulation period non-positive")
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result = [{} for i in self.all_ports]
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# Checking from not data_value to data_value
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self.write_delay_stimulus()
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self.stim.run_sim() #running sim prodoces spice output file.
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for port in self.targ_read_ports:
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bitlines_meas_vals = {}
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for mname in self.bitline_meas_names:
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bitlines_meas_vals[mname] = parse_spice_list("timing", mname)
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#Check that power parsing worked.
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for name, val in bitlines_meas_vals.items():
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if type(val)!=float:
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debug.error("Failed to Parse Bitline Values:\n\t\t{0}".format(bitlines_meas_vals),1) #Printing the entire dict looks bad.
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result[port].update(bitlines_meas_vals)
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# The delay is from the negative edge for our SRAM
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return (True,result)
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def analyze(self, probe_address, probe_data, slews, loads):
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"""Measures the bitline swing of the differential bitlines (bl/br) at 50% s_en """
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self.set_probe(probe_address, probe_data)
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self.load=max(loads)
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self.slew=max(slews)
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port = 0
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bitline_swings = {}
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self.targ_read_ports = [self.read_ports[port]]
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self.targ_write_ports = [self.write_ports[port]]
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debug.info(1,"Bitline swing test: corner {}".format(self.corner))
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(success, results)=self.run_delay_simulation()
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debug.check(success, "Bitline Failed: period {}".format(self.period))
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for mname in self.bitline_meas_names:
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bitline_swings[mname] = results[port][mname]
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debug.info(1,"Bitline values (bl/br): {}".format(bitline_swings))
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return bitline_swings
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