mirror of https://github.com/VLSIDA/OpenRAM.git
871 lines
42 KiB
HCL
871 lines
42 KiB
HCL
; Generated on Sep 28 16:05:23 1998
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; with @(#)$CDS: icfb.exe version 4.4.1 06/17/98 23:40 (cds10067) $
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;
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; Matt Clapp fixed: October 10, 2002
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; added via devices, deleted useless app-specific crap,
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; added lxExtractRules so undo in layout editor doesn't
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; complain.
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;********************************
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; LAYER DEFINITION
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;********************************
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layerDefinitions(
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techLayers(
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;( LayerName Layer# Abbreviation )
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;( --------- ------ ------------ )
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;User-Defined Layers:
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( P2Con 3 P2Con )
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( Poly2 7 Poly2 )
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( Pbase 10 Pbase )
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( Resistor 16 Resisto )
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( Capacitor 17 Capacit )
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( Diode 18 Diode )
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( SiBlock 29 SiBlock )
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( HR 34 HR )
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( Pwell 41 Pwell )
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( Nwell 42 Nwell )
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( Active 43 Active )
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( Pselect 44 Pselect )
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( Nselect 45 Nselect )
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( Poly1 46 Poly1 )
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( P1Con 47 P1Con )
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( ActX 48 ActX )
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( Metal1 49 Metal1 )
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( Via 50 Via )
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( Metal2 51 Metal2 )
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( Glass 52 Glass )
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( CapWell 59 CapWell )
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( XP 60 XP )
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( Via2 61 Via2 )
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( Metal3 62 Metal3 )
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( Via3 30 Via3 )
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( Metal4 31 Metal4 )
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( A1 80 A1 )
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( A2 81 A2 )
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( comment 117 comment )
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;System-Reserved Layers:
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( Unrouted 200 Unroute )
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( Row 201 Row )
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( Group 202 Group )
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( Cannotoccupy 203 Cannoto )
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( Canplace 204 Canplac )
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( hardFence 205 hardFen )
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( softFence 206 softFen )
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( y0 207 y0 )
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( y1 208 y1 )
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( y2 209 y2 )
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( y3 210 y3 )
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( y4 211 y4 )
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( y5 212 y5 )
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( y6 213 y6 )
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( y7 214 y7 )
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( y8 215 y8 )
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( y9 216 y9 )
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( designFlow 217 designF )
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( stretch 218 stretch )
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( edgeLayer 219 edgeLay )
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( changedLayer 220 changed )
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( unset 221 unset )
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( unknown 222 unknown )
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( spike 223 spike )
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( hiz 224 hiz )
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( resist 225 resist )
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( drive 226 drive )
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( supply 227 supply )
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( wire 228 wire )
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( pin 229 pin )
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( text 230 text )
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( device 231 device )
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( border 232 border )
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( snap 233 snap )
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( align 234 align )
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( prBoundary 235 prBound )
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( instance 236 instanc )
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( annotate 237 annotat )
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( marker 238 marker )
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( select 239 select )
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( grid 251 grid )
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( axis 252 axis )
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( hilite 253 hilite )
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( background 254 backgro )
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) ;techLayers
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techPurposes(
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;( PurposeName Purpose# Abbreviation )
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;( ----------- -------- ------------ )
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;User-Defined Purposes:
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;System-Reserved Purposes:
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( warning 234 wng )
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( tool1 235 tl1 )
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( tool0 236 tl0 )
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( label 237 lbl )
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( flight 238 flt )
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( error 239 err )
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( annotate 240 ant )
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( drawing1 241 dr1 )
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( drawing2 242 dr2 )
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( drawing3 243 dr3 )
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( drawing4 244 dr4 )
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( drawing5 245 dr5 )
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( drawing6 246 dr6 )
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( drawing7 247 dr7 )
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( drawing8 248 dr8 )
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( drawing9 249 dr9 )
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( boundary 250 bnd )
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( pin 251 pin )
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( drawing 252 drw )
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( net 253 net )
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( cell 254 cel )
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( all 255 all )
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) ;techPurposes
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techLayerPurposePriorities(
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;layers are ordered from lowest to highest priority
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; (higher priority is drawn on top of lower priority)
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;( LayerName Purpose )
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;( --------- ------- )
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( background drawing )
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( grid drawing )
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( grid drawing1 )
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( Nwell drawing )
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( Pwell drawing )
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( CapWell drawing )
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( Pselect drawing )
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( Nselect drawing )
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( Active drawing )
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( ActX drawing )
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( SiBlock drawing )
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( HR drawing )
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( Poly1 drawing )
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( P1Con drawing )
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( Poly2 drawing )
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( P2Con drawing )
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( Metal1 drawing )
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( Via drawing )
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( Metal2 drawing )
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( Via2 drawing )
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( Metal3 drawing )
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( Via3 drawing )
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( Metal4 drawing )
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( annotate drawing )
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( annotate drawing1 )
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( annotate drawing2 )
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( annotate drawing3 )
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( annotate drawing4 )
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( annotate drawing5 )
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( annotate drawing6 )
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( annotate drawing7 )
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( annotate drawing8 )
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( annotate drawing9 )
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( Poly1 pin )
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( Metal1 pin )
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( Metal2 pin )
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( Metal3 pin )
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( Metal4 pin )
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( Glass drawing )
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( XP drawing )
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( prBoundary drawing )
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( prBoundary boundary )
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( instance drawing )
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( prBoundary label )
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( instance label )
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( Row drawing )
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( Nwell net )
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( align drawing )
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( Pwell net )
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( CapWell net )
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( hardFence drawing )
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( Active net )
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( softFence drawing )
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( Row label )
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( Group drawing )
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( Group label )
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( Cannotoccupy drawing )
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( Cannotoccupy boundary )
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( Canplace drawing )
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( ActX net )
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( A2 drawing )
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( A1 drawing )
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( comment drawing )
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( border drawing )
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( Pselect net )
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( Nselect net )
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( SiBlock net )
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( HR net )
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( wire drawing )
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( Poly1 net )
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( wire label )
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( P1Con net )
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( wire flight )
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( Metal1 net )
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( device annotate )
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( Metal2 net )
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( device label )
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( Via net )
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( Metal3 net )
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( Via2 net )
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( Metal4 net )
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( Via3 net )
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( pin label )
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( text drawing )
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( pin drawing )
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( text drawing1 )
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( pin annotate )
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( device drawing )
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( axis drawing )
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( edgeLayer drawing )
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( edgeLayer pin )
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( snap drawing )
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( stretch drawing )
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( y0 drawing )
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( y1 drawing )
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( y2 drawing )
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( y3 drawing )
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( y4 drawing )
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( y5 drawing )
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( y6 drawing )
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( y7 drawing )
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( y8 drawing )
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( y9 drawing )
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( hilite drawing )
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( hilite drawing1 )
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( hilite drawing2 )
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( hilite drawing3 )
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( hilite drawing4 )
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( hilite drawing5 )
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( hilite drawing6 )
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( hilite drawing7 )
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( hilite drawing8 )
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( hilite drawing9 )
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( select drawing )
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( drive drawing )
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( hiz drawing )
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( resist drawing )
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( spike drawing )
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( supply drawing )
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( unknown drawing )
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( unset drawing )
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( designFlow drawing )
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( designFlow drawing1 )
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( designFlow drawing2 )
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( designFlow drawing3 )
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( designFlow drawing4 )
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( designFlow drawing5 )
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( designFlow drawing6 )
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( designFlow drawing7 )
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( designFlow drawing8 )
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( designFlow drawing9 )
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( changedLayer tool0 )
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( changedLayer tool1 )
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( marker warning )
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( marker error )
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( device drawing1 )
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( Pbase drawing )
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( Pbase net )
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( Resistor net )
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( Resistor drawing )
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( Capacitor net )
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( Capacitor drawing )
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( Diode net )
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( Diode drawing )
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( Poly2 net )
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( P2Con net )
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( device drawing2 )
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( Unrouted drawing )
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( text drawing2 )
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( Unrouted drawing1 )
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( Unrouted drawing2 )
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( Unrouted drawing3 )
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( Unrouted drawing4 )
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( Unrouted drawing5 )
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( Unrouted drawing6 )
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( Unrouted drawing7 )
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( Unrouted drawing8 )
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( Unrouted drawing9 )
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) ;techLayerPurposePriorities
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techDisplays(
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;( LayerName Purpose Packet Vis Sel Con2ChgLy DrgEnbl Valid )
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;( --------- ------- ------ --- --- --------- ------- ----- )
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( background drawing background t nil nil nil nil )
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( grid drawing grid t nil nil nil nil )
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( grid drawing1 grid1 t nil nil nil nil )
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( Nwell drawing Nwell t t t t t )
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( Pwell drawing Pwell t t t t nil )
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( Active drawing Active t t t t t )
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( ActX drawing ActX t t t t t )
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( Pselect drawing Pselect t t t t t )
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( Nselect drawing Nselect t t t t t )
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( SiBlock drawing SiBlock t t t t t )
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( HR drawing HR t t t t t )
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( CapWell drawing CapWell t t t t t )
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( Poly1 drawing Poly1 t t t t t )
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( P1Con drawing P1Con t t t t t )
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( Metal1 drawing Metal1 t t t t t )
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( Via drawing Via t t t t t )
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( Metal2 drawing Metal2 t t t t t )
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( annotate drawing annotate t t nil t nil )
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( annotate drawing1 annotate1 t t nil t nil )
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( annotate drawing2 annotate2 t t nil t nil )
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( annotate drawing3 annotate3 t t nil t nil )
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( annotate drawing4 annotate4 t t nil t nil )
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( annotate drawing5 annotate5 t t nil t nil )
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( annotate drawing6 annotate6 t t nil t nil )
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( annotate drawing7 annotate7 t t nil t nil )
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( annotate drawing8 annotate8 t t nil t nil )
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( annotate drawing9 annotate9 t t nil t nil )
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( Via2 drawing Via2 t t t t t )
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( Metal3 drawing Metal3 t t t t t )
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( Via3 drawing Via3 t t t t t )
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( Metal4 drawing Metal4 t t t t t )
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( Glass drawing Glass t t t nil t )
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( XP drawing XP t t t nil t )
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( Metal1 pin Metal1Pin t t t nil t )
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( Metal2 pin Metal2Pin t t t nil t )
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( Metal3 pin Metal3Pin t t t nil t )
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( Metal4 pin Metal4Pin t t t nil t )
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( Poly1 pin Poly1Pin t t t nil t )
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( prBoundary drawing prBoundary t t nil t nil )
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( prBoundary boundary prBoundaryBnd t t nil t nil )
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( instance drawing instance t t nil t t )
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( prBoundary label prBoundaryLbl t t t t nil )
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( instance label instanceLbl t t t t nil )
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( Row drawing Row t t t t nil )
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( Nwell net NwellNet t t t nil nil )
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( align drawing align t t nil t nil )
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( Pwell net PwellNet t t t nil nil )
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( CapWell net CapWellNet t t t nil nil )
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( SiBlock net SiBlockNet t t t nil nil )
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( HR net HRnet t t t nil nil )
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( hardFence drawing hardFence t t t t nil )
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( Active net ActiveNet t t t nil nil )
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( softFence drawing softFence t t t t nil )
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( Row label RowLbl t t t t nil )
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( Group drawing Group t t t t nil )
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( Group label GroupLbl t t t t nil )
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( Cannotoccupy drawing Cannotoccupy t t t t nil )
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( Cannotoccupy boundary CannotoccupyBnd t t t t nil )
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( Canplace drawing Canplace t t t t nil )
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( ActX net ActXNet t t t nil nil )
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( A2 drawing A2 t t t t nil )
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( A1 drawing A1 t t t t nil )
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( comment drawing comment t t t t nil )
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( border drawing border t t t t nil )
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( Pselect net PselectNet t t t nil nil )
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( Nselect net NselectNet t t t nil nil )
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( wire drawing wire t t t t nil )
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( Poly1 net Poly1Net t t t nil nil )
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( wire label wireLbl t t t t nil )
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( P1Con net P1ConNet t t t nil nil )
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( wire flight wireFlt t t t t nil )
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( Metal1 net Metal1Net t t t nil nil )
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( device annotate deviceAnt t t t t nil )
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( Metal2 net Metal2Net t t t nil nil )
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( Metal3 net Metal3Net t t t nil nil )
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( Metal4 net Metal4Net t t t nil nil )
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( device label deviceLbl t t t t nil )
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( Via net ViaNet t t t nil nil )
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( Via2 net Via2Net t t t nil nil )
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( pin label pinLbl t t t t nil )
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( text drawing text t t t t t )
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( pin drawing pin t t t t nil )
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( text drawing1 text1 t t t t nil )
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( pin annotate pinAnt t t t t nil )
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( device drawing device t t t t nil )
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( axis drawing axis t t t t nil )
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( edgeLayer drawing edgeLayer t t nil t nil )
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( edgeLayer pin edgeLayerPin t t nil t nil )
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( snap drawing snap t t nil t nil )
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( stretch drawing stretch t t nil t nil )
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( y0 drawing y0 t t nil t nil )
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( y1 drawing y1 t t nil t nil )
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( y2 drawing y2 t t nil t nil )
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( y3 drawing y3 t t nil t nil )
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( y4 drawing y4 t t nil t nil )
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( y5 drawing y5 t t nil t nil )
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( y6 drawing y6 t t nil t nil )
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( y7 drawing y7 t t nil t nil )
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( y8 drawing y8 t t nil t nil )
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( y9 drawing y9 t t nil t nil )
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( hilite drawing hilite t t nil t nil )
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( hilite drawing1 hilite1 t t t t nil )
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( hilite drawing2 hilite2 t t nil t nil )
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( hilite drawing3 hilite3 t t t t nil )
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( hilite drawing4 hilite4 t t t t nil )
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( hilite drawing5 hilite5 t t t t nil )
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( hilite drawing6 hilite6 t t t t nil )
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( hilite drawing7 hilite7 t t t t nil )
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( hilite drawing8 hilite8 t t t t nil )
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( hilite drawing9 hilite9 t t t t nil )
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( select drawing select t t nil t nil )
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( drive drawing drive t t t t nil )
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( hiz drawing hiz t t t t nil )
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( resist drawing resist t t t t nil )
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( spike drawing spike t t t t nil )
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( supply drawing supply t t t t nil )
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( unknown drawing unknown t t t t nil )
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( unset drawing unset t t t t nil )
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( designFlow drawing designFlow t t t nil nil )
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( designFlow drawing1 designFlow1 t t t nil nil )
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( designFlow drawing2 designFlow2 t t t nil nil )
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( designFlow drawing3 designFlow3 t t t nil nil )
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( designFlow drawing4 designFlow4 t t t nil nil )
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( designFlow drawing5 designFlow5 t t t nil nil )
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( designFlow drawing6 designFlow6 t t t nil nil )
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( designFlow drawing7 designFlow7 t t t nil nil )
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( designFlow drawing8 designFlow8 t t t nil nil )
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( designFlow drawing9 designFlow9 t t t nil nil )
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( changedLayer tool0 changedLayerTl0 nil nil nil nil nil )
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( changedLayer tool1 changedLayerTl1 nil nil t nil nil )
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( marker warning markerWarn t t t t nil )
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( marker error markerErr t t t t nil )
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( device drawing1 device1 t t t t nil )
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( Poly2 net Poly2Net t t t nil nil )
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( Poly2 drawing Poly2 t t t t t )
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( P2Con net P2ConNet t t t nil nil )
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( P2Con drawing P2Con t t t t t )
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( Pbase net PbaseNet t t t nil nil )
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( Pbase drawing Pbase t t t t t )
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( Resistor net ResistorNet t t t nil nil )
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( Resistor drawing Resistor t t t t t )
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( Capacitor net CapacitorNet t t t nil nil )
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( Capacitor drawing Capacitor t t t t t )
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( Diode net DiodeNet t t t nil nil )
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( Diode drawing Diode t t t t t )
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( device drawing2 device2 t t t t nil )
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( Unrouted drawing Unrouted t t t t nil )
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( text drawing2 text2 t t t t nil )
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( Unrouted drawing1 Unrouted1 t t t t nil )
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( Unrouted drawing2 Unrouted2 t t t t nil )
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( Unrouted drawing3 Unrouted3 t t t t nil )
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( Unrouted drawing4 Unrouted4 t t t t nil )
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( Unrouted drawing5 Unrouted5 t t t t nil )
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( Unrouted drawing6 Unrouted6 t t t t nil )
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( Unrouted drawing7 Unrouted7 t t t t nil )
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( Unrouted drawing8 Unrouted8 t t t t nil )
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( Unrouted drawing9 Unrouted9 t t t t nil )
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) ;techDisplays
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; I don't think the following is necessary (or used!)
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techLayerProperties(
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;( PropName Layer1 [ Layer2 ] PropValue )
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( contactLimit P2Con 10000 )
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( eqPinLimit P2Con 10000 )
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( horizontalJogLength P2Con 2147483648.000000 )
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( routingGrid P2Con 1.000000 )
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( verticalJogLength P2Con 2147483648.000000 )
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( routingGrid Poly2 1.000000 )
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( contactLimit Active 10000 )
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( eqPinLimit Active 10000 )
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( horizontalJogLength Active 2147483648.000000 )
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( routingGrid Active 1.000000 )
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( verticalJogLength Active 2147483648.000000 )
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( routingGrid Poly1 1.000000 )
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( contactLimit P1Con 10000 )
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( eqPinLimit P1Con 10000 )
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( horizontalJogLength P1Con 2147483648.000000 )
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( routingGrid P1Con 1.000000 )
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( verticalJogLength P1Con 2147483648.000000 )
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( contactLimit ActX 10000 )
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( eqPinLimit ActX 10000 )
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( horizontalJogLength ActX 2147483648.000000 )
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( routingGrid ActX 1.000000 )
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( verticalJogLength ActX 2147483648.000000 )
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( routingGrid Metal1 1.000000 )
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( contactLimit Via 10000 )
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( eqPinLimit Via 10000 )
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( horizontalJogLength Via 2147483648.000000 )
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( routingGrid Via 1.000000 )
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( verticalJogLength Via 2147483648.000000 )
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( routingGrid Metal2 1.000000 )
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)
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) ;layerDefinitions
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;********************************
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; DEVICE RULES
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;********************************
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devices(
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tcCreateCDSDeviceClass()
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symContactDevice(
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;( deviceName viaLayer viaPurpose
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( VIA Via drawing
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; layer1 purpose1 [implant1]
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Metal1 drawing
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; layer2 purpose2 [implant2]
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Metal2 drawing
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; width length [( row column xPitch yPitch xBias yBias )]
|
|
; 2 2 ( 1 1 _NA_ _NA_ _NA_ _NA_ )
|
|
2 2
|
|
|
|
; encLayer1 encLayer2 legalRegion )
|
|
1 1 _NA_)
|
|
) ;symContactDevice
|
|
|
|
symContactDevice(
|
|
;( deviceName viaLayer viaPurpose
|
|
( VIA2 Via2 drawing
|
|
|
|
; layer1 purpose1 [implant1]
|
|
Metal2 drawing
|
|
|
|
; layer2 purpose2 [implant2]
|
|
Metal3 drawing
|
|
|
|
; width length [( row column xPitch yPitch xBias yBias )]
|
|
; 2 2 ( 1 1 _NA_ _NA_ _NA_ _NA_ )
|
|
2 2
|
|
|
|
; encLayer1 encLayer2 legalRegion )
|
|
1 2 _NA_)
|
|
) ;symContactDevice
|
|
|
|
) ;devices
|
|
|
|
|
|
;********************************
|
|
; LAYER RULES
|
|
;********************************
|
|
|
|
layerRules(
|
|
streamLayers(
|
|
;( layer streamNumber dataType translate )
|
|
;( ----- ------------ -------- --------- )
|
|
( ("background" "drawing") 0 0 nil )
|
|
( ("grid" "drawing") 0 0 nil )
|
|
( ("grid" "drawing1") 0 0 nil )
|
|
( ("Nwell" "drawing") 42 0 t )
|
|
( ("Pwell" "drawing") 41 0 t )
|
|
( ("Active" "drawing") 43 0 t )
|
|
( ("ActX" "drawing") 48 0 t )
|
|
( ("Pselect" "drawing") 44 0 t )
|
|
( ("Nselect" "drawing") 45 0 t )
|
|
( ("Poly1" "drawing") 46 0 t )
|
|
( ("P1Con" "drawing") 47 0 t )
|
|
( ("Metal1" "drawing") 49 0 t )
|
|
( ("Metal2" "drawing") 51 0 t )
|
|
( ("Metal3" "drawing") 62 0 t )
|
|
( ("Metal4" "drawing") 31 0 t )
|
|
( ("annotate" "drawing") 0 0 nil )
|
|
( ("annotate" "drawing1") 0 0 nil )
|
|
( ("annotate" "drawing2") 0 0 nil )
|
|
( ("annotate" "drawing3") 0 0 nil )
|
|
( ("annotate" "drawing4") 0 0 nil )
|
|
( ("annotate" "drawing5") 0 0 nil )
|
|
( ("annotate" "drawing6") 0 0 nil )
|
|
( ("annotate" "drawing7") 0 0 nil )
|
|
( ("annotate" "drawing8") 0 0 nil )
|
|
( ("annotate" "drawing9") 0 0 nil )
|
|
( ("Glass" "drawing") 52 0 t )
|
|
( ("XP" "drawing") 60 0 t )
|
|
( ("Metal2" "pin") 0 0 nil )
|
|
( ("Poly1" "pin") 0 0 nil )
|
|
( ("prBoundary" "drawing") 0 0 nil )
|
|
( ("Metal1" "pin") 0 0 nil )
|
|
( ("prBoundary" "boundary") 0 0 nil )
|
|
( ("instance" "drawing") 246 0 nil )
|
|
( ("instance" "label") 0 0 nil )
|
|
( ("Nwell" "net") 0 0 nil )
|
|
( ("align" "drawing") 0 0 nil )
|
|
( ("Pwell" "net") 0 0 nil )
|
|
( ("hardFence" "drawing") 0 0 nil )
|
|
( ("Active" "net") 0 0 nil )
|
|
( ("softFence" "drawing") 0 0 nil )
|
|
( ("ActX" "net") 0 0 nil )
|
|
( ("A2" "drawing") 5 0 nil )
|
|
( ("A1" "drawing") 2 0 nil )
|
|
( ("comment" "drawing") 0 0 nil )
|
|
( ("border" "drawing") 0 0 nil )
|
|
( ("Pselect" "net") 0 0 nil )
|
|
( ("Nselect" "net") 0 0 nil )
|
|
( ("wire" "drawing") 0 0 nil )
|
|
( ("Poly1" "net") 0 0 nil )
|
|
( ("P1Con" "net") 0 0 nil )
|
|
( ("Metal1" "net") 0 0 nil )
|
|
( ("Metal2" "net") 0 0 nil )
|
|
( ("Metal3" "net") 0 0 nil )
|
|
( ("Metal4" "net") 0 0 nil )
|
|
( ("device" "label") 0 0 nil )
|
|
( ("pin" "label") 0 0 nil )
|
|
( ("text" "drawing") 63 0 t )
|
|
( ("pin" "drawing") 0 0 nil )
|
|
( ("device" "drawing") 0 0 nil )
|
|
( ("axis" "drawing") 0 0 nil )
|
|
( ("edgeLayer" "drawing") 0 0 nil )
|
|
( ("edgeLayer" "pin") 0 0 nil )
|
|
( ("snap" "drawing") 0 0 nil )
|
|
( ("stretch" "drawing") 0 0 nil )
|
|
( ("y0" "drawing") 0 0 nil )
|
|
( ("y1" "drawing") 0 0 nil )
|
|
( ("y2" "drawing") 0 0 nil )
|
|
( ("y3" "drawing") 0 0 nil )
|
|
( ("y4" "drawing") 0 0 nil )
|
|
( ("y5" "drawing") 0 0 nil )
|
|
( ("y6" "drawing") 0 0 nil )
|
|
( ("y7" "drawing") 0 0 nil )
|
|
( ("y8" "drawing") 0 0 nil )
|
|
( ("y9" "drawing") 0 0 nil )
|
|
( ("hilite" "drawing") 0 0 nil )
|
|
( ("hilite" "drawing2") 0 0 nil )
|
|
( ("select" "drawing") 0 0 nil )
|
|
( ("drive" "drawing") 0 0 nil )
|
|
( ("hiz" "drawing") 0 0 nil )
|
|
( ("resist" "drawing") 0 0 nil )
|
|
( ("spike" "drawing") 0 0 nil )
|
|
( ("supply" "drawing") 0 0 nil )
|
|
( ("unknown" "drawing") 0 0 nil )
|
|
( ("unset" "drawing") 0 0 nil )
|
|
( ("changedLayer" "tool0") 0 0 nil )
|
|
( ("Resistor" "net") 0 0 nil )
|
|
( ("Resistor" "drawing") 0 0 nil )
|
|
( ("Capacitor" "net") 0 0 nil )
|
|
( ("Capacitor" "drawing") 0 0 nil )
|
|
( ("Diode" "net") 0 0 nil )
|
|
( ("Diode" "drawing") 0 0 nil )
|
|
( ("Poly2" "net") 0 0 nil )
|
|
( ("Poly2" "drawing") 0 0 nil )
|
|
( ("P2Con" "net") 0 0 nil )
|
|
( ("P2Con" "drawing") 0 0 nil )
|
|
( ("Pbase" "drawing") 0 0 nil )
|
|
( ("Pbase" "net") 0 0 nil )
|
|
( P2Con 0 0 nil )
|
|
( Poly2 0 0 nil )
|
|
( Pwell 0 0 nil )
|
|
( Nwell 0 0 nil )
|
|
( Active 0 0 nil )
|
|
( Pselect 0 0 nil )
|
|
( Nselect 0 0 nil )
|
|
( Poly1 0 0 nil )
|
|
( P1Con 0 0 nil )
|
|
( ActX 0 0 nil )
|
|
( Metal1 0 0 nil )
|
|
( Via 0 0 nil )
|
|
( Metal2 0 0 nil )
|
|
( Glass 0 0 nil )
|
|
( XP 0 0 nil )
|
|
( ("Via" "drawing") 50 0 t )
|
|
( ("Via" "net") 0 0 nil )
|
|
( ("Via2" "drawing") 61 0 t )
|
|
( ("Via2" "net") 0 0 nil )
|
|
( ("Via3" "drawing") 30 0 t )
|
|
( ("Via3" "net") 0 0 nil )
|
|
( ("CapWell" "drawing") 0 0 nil )
|
|
( ("CapWell" "net") 0 0 nil )
|
|
( ("SiBlock" "drawing") 0 0 nil )
|
|
( ("SiBlock" "net") 0 0 nil )
|
|
( ("HR" "drawing") 0 0 nil )
|
|
( ("HR" "net") 0 0 nil )
|
|
) ;streamLayers
|
|
|
|
viaLayers(
|
|
;( layer1 viaLayer layer2 )
|
|
;( ------ -------- ------ )
|
|
( Metal3 Via3 Metal4 )
|
|
( Metal2 Via2 Metal3 )
|
|
( Metal1 Via Metal2 )
|
|
( Active ActX Poly1 )
|
|
( Poly1 P1Con Metal1 )
|
|
( Poly2 P2Con Metal1 )
|
|
) ;viaLayers
|
|
|
|
) ;layerRules
|
|
|
|
|
|
;********************************
|
|
; PHYSICAL RULES
|
|
;********************************
|
|
|
|
physicalRules(
|
|
orderedSpacingRules(
|
|
;( rule layer1 layer2 value )
|
|
;( ---- ------ ------ ----- )
|
|
( minEnclosure "prBoundary" "Metal1" 0.0 )
|
|
( minEnclosure "Metal2" "Via" 1.0 )
|
|
( minEnclosure "Metal1" "Via" 1.0 )
|
|
( minEnclosure "Metal1" "P1Con" 1.0 )
|
|
( minEnclosure "Metal1" "ActX" 1.0 )
|
|
( minEnclosure "Nselect" "Active" 2.0 )
|
|
( minEnclosure "Pselect" "Active" 2.0 )
|
|
( minEnclosure "Active" "ActX" 1.0 )
|
|
( minEnclosure "Pwell" "Active" 5.0 )
|
|
( minEnclosure "Nwell" "Active" 5.0 )
|
|
) ;orderedSpacingRules
|
|
|
|
spacingRules(
|
|
;( rule layer1 layer2 value )
|
|
;( ---- ------ ------ ----- )
|
|
( minSpacing "P2Con" 2.0 )
|
|
( minSpacing "Poly2" 3.0 )
|
|
( minSpacing "Pwell" 9.0 )
|
|
( minSpacing "Nwell" 9.0 )
|
|
( minSpacing "Active" 3.0 )
|
|
( minSpacing "Pselect" 2.0 )
|
|
( minSpacing "Nselect" 2.0 )
|
|
( minSpacing "Poly1" 2.0 )
|
|
( minSpacing "P1Con" 2.0 )
|
|
( minSpacing "ActX" 2.0 )
|
|
( minSpacing "Metal1" 3.0 )
|
|
( minSpacing "Via" 3.0 )
|
|
( minSpacing "Via2" 3.0 )
|
|
( minSpacing "Metal2" 3.0 )
|
|
( minSpacing "Metal3" 4.0 )
|
|
( minSpacing "Glass" 75.0 )
|
|
( minSpacing "XP" 100.0 )
|
|
( minSpacing "Metal2" 4.0 )
|
|
( minSpacing "P1Con" "Via" 2.0 )
|
|
( minSpacing "ActX" "Via" 2.0 )
|
|
( minSpacing "ActX" "P2Con" 2.0 )
|
|
( minSpacing "Poly2" "P2Con" 4.0 )
|
|
( minSpacing "Poly1" "P1Con" 4.0 )
|
|
( minSpacing "ActX" "P1Con" 2.0 )
|
|
( minSpacing "Active" "P1Con" 2.0 )
|
|
( minSpacing "Active" "Poly2" 2.0 )
|
|
( minSpacing "Poly1" "Poly2" 2.0 )
|
|
( minSpacing "Active" "Poly1" 2.0 )
|
|
( minSpacing "ActX" "Poly1" 2.0 )
|
|
( minSpacing "Pselect" "Nselect" 0.0 )
|
|
( minSpacing "Nwell" "Pwell" 9.0 )
|
|
( minWidth "P2Con" 2.0 )
|
|
( minWidth "Poly2" 3.0 )
|
|
( minWidth "Pwell" 10.0 )
|
|
( minWidth "Nwell" 10.0 )
|
|
( minWidth "Active" 3.0 )
|
|
( minWidth "Pselect" 2.0 )
|
|
( minWidth "Nselect" 2.0 )
|
|
( minWidth "Poly1" 2.0 )
|
|
( minWidth "P1Con" 2.0 )
|
|
( minWidth "ActX" 2.0 )
|
|
( minWidth "Metal1" 4.0 )
|
|
( minWidth "Via" 2.0 )
|
|
( minWidth "Metal2" 4.0 )
|
|
( minWidth "Glass" 75.0 )
|
|
( minWidth "XP" 100.0 )
|
|
( minWidth "Metal3" 6.0 )
|
|
) ;spacingRules
|
|
|
|
mfgGridResolution(
|
|
( 1.000000 )
|
|
) ;mfgGridResolution
|
|
|
|
) ;physicalRules
|
|
|
|
|
|
;********************************
|
|
; ELECTRICAL RULES
|
|
;********************************
|
|
|
|
electricalRules(
|
|
characterizationRules(
|
|
;( rule layer1 layer2 value )
|
|
;( ---- ------ ------ ----- )
|
|
( areaCap "P2Con" 0.0 )
|
|
( areaCap "Poly2" 0.0 )
|
|
( areaCap "Active" 0.0 )
|
|
( areaCap "Poly1" 6e-05 )
|
|
( areaCap "P1Con" 0.0 )
|
|
( areaCap "ActX" 0.0 )
|
|
( areaCap "Metal1" 2.6e-05 )
|
|
( areaCap "Via" 0.0 )
|
|
( areaCap "Metal2" 1.6e-05 )
|
|
( edgeCapacitance "P2Con" 0.0 )
|
|
( edgeCapacitance "Poly2" 0.0 )
|
|
( edgeCapacitance "Active" 0.0 )
|
|
( edgeCapacitance "Poly1" 0.0 )
|
|
( edgeCapacitance "P1Con" 0.0 )
|
|
( edgeCapacitance "ActX" 0.0 )
|
|
( edgeCapacitance "Metal1" 0.0 )
|
|
( edgeCapacitance "Via" 0.0 )
|
|
( edgeCapacitance "Metal2" 0.0 )
|
|
( sheetRes "P2Con" 0.0 )
|
|
( sheetRes "Poly2" 0.0 )
|
|
( sheetRes "Active" 0.0 )
|
|
( sheetRes "Poly1" 23.0 )
|
|
( sheetRes "P1Con" 0.0 )
|
|
( sheetRes "ActX" 0.0 )
|
|
( sheetRes "Metal1" 0.04 )
|
|
( sheetRes "Via" 0.0 )
|
|
( sheetRes "Metal2" 0.07 )
|
|
( currentDensity "P2Con" 1.0 )
|
|
( currentDensity "Poly2" 1.0 )
|
|
( currentDensity "Active" 1.0 )
|
|
( currentDensity "Poly1" 1.0 )
|
|
( currentDensity "P1Con" 1.0 )
|
|
( currentDensity "ActX" 1.0 )
|
|
( currentDensity "Metal1" 1.0 )
|
|
( currentDensity "Via" 1.0 )
|
|
( currentDensity "Metal2" 1.0 )
|
|
( currentDensity "Via2" 1.0 )
|
|
( currentDensity "Metal3" 1.0 )
|
|
( currentDensity "Via3" 1.0 )
|
|
( currentDensity "Metal4" 1.0 )
|
|
) ;characterizationRules
|
|
|
|
) ;electricalRules
|
|
|
|
|
|
;********************************
|
|
; LAYOUT EDITOR RULES
|
|
;********************************
|
|
; specifies the ordering of the layers in the LSW
|
|
|
|
leRules(
|
|
leLswLayers(
|
|
;( layer purpose )
|
|
; ----- ------- )
|
|
( Nwell drawing )
|
|
( Pselect drawing )
|
|
( Nselect drawing )
|
|
( Active drawing )
|
|
( ActX drawing )
|
|
( Poly1 drawing )
|
|
( P1Con drawing )
|
|
( Metal1 drawing )
|
|
( Via drawing )
|
|
( Metal2 drawing )
|
|
( Via2 drawing )
|
|
( Metal3 drawing )
|
|
( Via3 drawing )
|
|
( Metal4 drawing )
|
|
( Poly1 pin )
|
|
( Metal1 pin )
|
|
( Metal2 pin )
|
|
( Metal3 pin )
|
|
( Metal4 pin )
|
|
( Poly2 drawing )
|
|
( P2Con drawing )
|
|
( instance drawing )
|
|
( text drawing )
|
|
( CapWell drawing )
|
|
( SiBlock drawing )
|
|
( HR drawing )
|
|
( Pbase drawing )
|
|
( Resistor drawing )
|
|
( Capacitor drawing )
|
|
( Diode drawing )
|
|
( Glass drawing )
|
|
( XP drawing )
|
|
|
|
) ;leLswLayers
|
|
) ;leRules
|
|
|
|
|
|
;********************************
|
|
; VIRTUOSO XL RULES
|
|
;********************************
|
|
; specifies the ordering of the layers in the LSW
|
|
|
|
lxRules(
|
|
lxExtractLayers(
|
|
(Metal1 Metal2 Metal3 Metal4)
|
|
) ;lxExtractLayers
|
|
) ;lxRules
|
|
|