mirror of https://github.com/VLSIDA/OpenRAM.git
16 lines
359 B
SourcePawn
16 lines
359 B
SourcePawn
|
|
.SUBCKT cell_1rw bl br wl vdd gnd
|
|
* Inverter 1
|
|
MM0 Q_bar Q gnd gnd NMOS_VTG W=205.00n L=50n
|
|
MM4 Q_bar Q vdd vdd PMOS_VTG W=90n L=50n
|
|
|
|
* Inverer 2
|
|
MM1 Q Q_bar gnd gnd NMOS_VTG W=205.00n L=50n
|
|
MM5 Q Q_bar vdd vdd PMOS_VTG W=90n L=50n
|
|
|
|
* Access transistors
|
|
MM3 bl wl Q gnd NMOS_VTG W=135.00n L=50n
|
|
MM2 br wl Q_bar gnd NMOS_VTG W=135.00n L=50n
|
|
.ENDS cell_1rw
|
|
|