mirror of https://github.com/VLSIDA/OpenRAM.git
104 lines
1.3 KiB
Verilog
104 lines
1.3 KiB
Verilog
`define assert(signal, value) \
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if (!(signal === value)) begin \
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$display("ASSERTION FAILED in %m: signal != value"); \
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$finish;\
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end
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module sram_1rw_tb;
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reg clk;
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reg [3:0] addr0;
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reg [1:0] din0;
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reg csb0;
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reg web0;
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wire [1:0] dout0;
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sram_2_16_scn4m_subm U0 (.din0(din0),
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.dout0(dout0),
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.addr0(addr0),
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.csb0(csb0),
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.web0(web0),
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.clk0(clk)
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);
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initial
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begin
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//$monitor("%g addr0=%b din0=%b dout0=%b",
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// $time, addr0, din0, dout0);
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clk = 1;
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csb0 = 1;
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web0 = 1;
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addr0 = 0;
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din0 = 0;
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// write
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#10 din0=2'b10;
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addr0=4'h1;
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web0 = 0;
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csb0 = 0;
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// write another
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#10 din0=2'b01;
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addr0=4'hC;
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web0 = 0;
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csb0 = 0;
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// read undefined
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#10 din0=2'b11;
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addr0=4'h0;
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web0 = 1;
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csb0 = 0;
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#10 `assert(dout0, 2'bxx)
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// read defined
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din0=2'b11;
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addr0=4'hC;
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web0 = 1;
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csb0 = 0;
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#10 `assert(dout0, 2'b01)
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// write another
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din0=2'b11;
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addr0=4'hA;
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web0 = 0;
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csb0 = 0;
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// read defined
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#10 din0=2'b11;
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addr0=4'h1;
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web0 = 1;
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csb0 = 0;
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#10 `assert(dout0, 2'b10)
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// read defined
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din0=2'b11;
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addr0=4'hA;
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web0 = 1;
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csb0 = 0;
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#10 `assert(dout0, 2'b11)
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// read undefined
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din0=2'b11;
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addr0=4'h0;
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web0 = 1;
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csb0 = 0;
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#10 `assert(dout0, 2'bxx)
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#10 $finish;
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end
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always
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#5 clk = !clk;
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endmodule
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