mirror of https://github.com/VLSIDA/OpenRAM.git
291 lines
11 KiB
Python
291 lines
11 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2024 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from openram import debug
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from openram.base import design
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from openram.base import vector
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from openram.sram_factory import factory
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from openram.tech import parameter, drc
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from openram.tech import cell_properties as cell_props
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from openram import OPTS
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from .pgate import *
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class precharge(design):
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"""
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Creates a single precharge cell
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This module implements the precharge bitline cell used in the design.
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"""
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def __init__(self, name, size=1, bitcell_bl="bl", bitcell_br="br"):
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debug.info(2, "creating precharge cell {0}".format(name))
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super().__init__(name)
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self.bitcell = factory.create(module_type=OPTS.bitcell)
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self.beta = parameter["beta"]
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self.ptx_width = self.beta * parameter["min_tx_size"]
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self.ptx_mults = 1
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if(cell_props.use_strap == True and OPTS.num_ports == 1):
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strap = factory.create(module_type=cell_props.strap_module, version=cell_props.strap_version)
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self.width = self.bitcell.width + strap.width
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else:
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self.width = self.bitcell.width
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self.bitcell_bl = bitcell_bl
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self.bitcell_br = bitcell_br
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self.bitcell_bl_pin =self.bitcell.get_pin(self.bitcell_bl)
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self.bitcell_br_pin =self.bitcell.get_pin(self.bitcell_br)
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if self.bitcell_bl_pin.layer == "m1":
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self.bitline_layer = "m1"
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self.en_layer = "m2"
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else:
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self.bitline_layer = "m2"
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self.en_layer = "m1"
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# Creates the netlist and layout
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# Since it has variable height, it is not a pgate.
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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self.DRC_LVS()
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def get_bl_names(self):
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return "bl"
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def get_br_names(self):
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return "br"
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def create_netlist(self):
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self.add_pins()
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self.add_ptx()
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self.create_ptx()
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def create_layout(self):
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self.place_ptx()
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self.connect_poly()
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self.route_en()
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self.place_nwell_and_contact()
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self.route_supplies()
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self.route_bitlines()
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self.connect_to_bitlines()
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self.add_boundary()
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def add_pins(self):
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self.add_pin_list(["bl", "br", "en_bar", "vdd"],
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["OUTPUT", "OUTPUT", "INPUT", "POWER"])
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def add_ptx(self):
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"""
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Initializes the upper and lower pmos
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"""
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if cell_props.ptx.bin_spice_models:
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self.ptx_width = pgate.nearest_bin("pmos", self.ptx_width)
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self.pmos = factory.create(module_type="ptx",
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width=self.ptx_width,
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mults=self.ptx_mults,
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tx_type="pmos")
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def route_supplies(self):
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"""
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Adds a vdd rail at the top of the cell
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"""
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pmos_pin = self.upper_pmos2_inst.get_pin("S")
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pmos_pos = pmos_pin.center()
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self.add_path(pmos_pin.layer, [pmos_pos, self.well_contact_pos])
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self.add_layout_pin_rect_center(text="vdd",
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layer=pmos_pin.layer,
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offset=self.well_contact_pos)
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def create_ptx(self):
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"""
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Create both the upper_pmos and lower_pmos to the module
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"""
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self.lower_pmos_inst = self.add_inst(name="lower_pmos",
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mod=self.pmos)
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self.connect_inst(["bl", "en_bar", "br", "vdd"])
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self.upper_pmos1_inst = self.add_inst(name="upper_pmos1",
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mod=self.pmos)
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self.connect_inst(["bl", "en_bar", "vdd", "vdd"])
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self.upper_pmos2_inst = self.add_inst(name="upper_pmos2",
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mod=self.pmos)
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self.connect_inst(["br", "en_bar", "vdd", "vdd"])
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def place_ptx(self):
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"""
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Place both the upper_pmos and lower_pmos to the module
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"""
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# reserve some offset to jog the bitlines
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self.initial_yoffset = self.pmos.active_offset.y + self.m2_pitch
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# Compute the other pmos2 location,
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# but determining offset to overlap the source and drain pins
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overlap_offset = self.pmos.get_pin("D").ll() - self.pmos.get_pin("S").ll()
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# adds the lower pmos to layout
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self.lower_pmos_position = vector(self.well_enclose_active + 0.5 * self.m1_width,
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self.initial_yoffset)
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self.lower_pmos_inst.place(self.lower_pmos_position)
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# adds the upper pmos(s) to layout with 2 M2 tracks
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ydiff = self.pmos.height + 2 * self.m2_pitch
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self.upper_pmos1_pos = self.lower_pmos_position + vector(0, ydiff)
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self.upper_pmos1_inst.place(self.upper_pmos1_pos)
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# Second pmos to the right of the first
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upper_pmos2_pos = self.upper_pmos1_pos + overlap_offset
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self.upper_pmos2_inst.place(upper_pmos2_pos)
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def connect_poly(self):
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"""
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Connects the upper and lower pmos together
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"""
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offset = self.lower_pmos_inst.get_pin("G").ul()
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# connects the top and bottom pmos' gates together
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ylength = self.upper_pmos1_inst.get_pin("G").ll().y - offset.y
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self.add_rect(layer="poly",
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offset=offset,
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width=self.poly_width,
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height=ylength)
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# connects the two poly for the two upper pmos(s)
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offset = offset + vector(0, ylength - self.poly_width)
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xlength = self.upper_pmos2_inst.get_pin("G").lx() \
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- self.upper_pmos1_inst.get_pin("G").lx() \
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+ self.poly_width
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self.add_rect(layer="poly",
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offset=offset,
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width=xlength,
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height=self.poly_width)
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def route_en(self):
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"""
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Adds the en input rail, en contact/vias, and connects to the pmos
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"""
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# adds the en contact to connect the gates to the en rail
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pin_offset = self.lower_pmos_inst.get_pin("G").lr()
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# This is an extra space down for some techs with contact to active spacing
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contact_space = max(self.poly_space,
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self.poly_contact_to_gate) + 0.5 * self.poly_contact.first_layer_height
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offset = pin_offset - vector(0, contact_space)
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self.add_via_stack_center(from_layer="poly",
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to_layer=self.en_layer,
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offset=offset)
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self.add_path("poly",
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[self.lower_pmos_inst.get_pin("G").bc(), offset])
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# adds the en rail
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self.add_layout_pin_segment_center(text="en_bar",
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layer=self.en_layer,
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start=offset.scale(0, 1),
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end=offset.scale(0, 1) + vector(self.width, 0))
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def place_nwell_and_contact(self):
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"""
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Adds a nwell tap to connect to the vdd rail
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"""
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# adds the contact from active to metal1
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offset_height = self.upper_pmos1_inst.uy() + \
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self.active_contact.height + \
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self.nwell_extend_active
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self.well_contact_pos = self.upper_pmos1_inst.get_pin("D").center().scale(1, 0) + \
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vector(0, offset_height)
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self.well_contact = self.add_via_center(layers=self.active_stack,
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offset=self.well_contact_pos,
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implant_type="n",
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well_type="n")
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self.add_via_stack_center(from_layer=self.active_stack[2],
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to_layer=self.bitline_layer,
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offset=self.well_contact_pos)
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self.height = self.well_contact_pos.y + self.active_contact.height + self.m1_space
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# nwell should span the whole design since it is pmos only
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self.add_rect(layer="nwell",
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offset=vector(0, 0),
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width=self.width,
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height=self.height)
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def route_bitlines(self):
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"""
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Adds both bit-line and bit-line-bar to the module
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"""
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layer_pitch = getattr(self, "{}_pitch".format(self.bitline_layer))
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# adds the BL
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self.bl_xoffset = layer_pitch
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top_pos = vector(self.bl_xoffset, self.height)
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pin_pos = vector(self.bl_xoffset, 0)
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self.add_path(self.bitline_layer, [top_pos, pin_pos])
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self.bl_pin = self.add_layout_pin_segment_center(text="bl",
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layer=self.bitline_layer,
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start=pin_pos,
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end=top_pos)
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# adds the BR
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self.br_xoffset = self.width - layer_pitch
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top_pos = vector(self.br_xoffset, self.height)
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pin_pos = vector(self.br_xoffset, 0)
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self.add_path(self.bitline_layer, [top_pos, pin_pos])
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self.br_pin = self.add_layout_pin_segment_center(text="br",
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layer=self.bitline_layer,
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start=pin_pos,
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end=top_pos)
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def connect_to_bitlines(self):
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"""
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Connect the bitlines to the devices
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"""
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self.add_bitline_contacts()
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self.connect_pmos(self.lower_pmos_inst.get_pin("S"),
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self.bl_xoffset)
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self.connect_pmos(self.lower_pmos_inst.get_pin("D"),
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self.br_xoffset)
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self.connect_pmos(self.upper_pmos1_inst.get_pin("S"),
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self.bl_xoffset)
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self.connect_pmos(self.upper_pmos2_inst.get_pin("D"),
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self.br_xoffset)
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def add_bitline_contacts(self):
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"""
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Adds contacts/via from metal1 to metal2 for bit-lines
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"""
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# BL
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for lower_pin in [self.lower_pmos_inst.get_pin("S"), self.lower_pmos_inst.get_pin("D")]:
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self.add_via_stack_center(from_layer=lower_pin.layer,
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to_layer=self.bitline_layer,
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offset=lower_pin.center(),
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directions=("V", "V"))
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# BR
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for upper_pin in [self.upper_pmos1_inst.get_pin("S"), self.upper_pmos2_inst.get_pin("D")]:
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self.add_via_stack_center(from_layer=upper_pin.layer,
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to_layer=self.bitline_layer,
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offset=upper_pin.center(),
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directions=("V", "V"))
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def connect_pmos(self, pmos_pin, bit_xoffset):
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"""
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Connect a pmos pin to bitline pin
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"""
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left_pos = vector(min(pmos_pin.cx(), bit_xoffset), pmos_pin.cy())
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right_pos = vector(max(pmos_pin.cx(), bit_xoffset), pmos_pin.cy())
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self.add_path(self.bitline_layer,
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[left_pos, right_pos],
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width=pmos_pin.height())
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