mrg d609e4ea04 Reimplement trim options (except on unit tests). ... Allow trim netlist to be used for delay and functional simulation. Each class implements a "trim_insts" set of instances that can be removed. By default far left, right, top and bottom cells in the bitcell arrays are kept. Use lvs option in sp_write Fix lvs option in sram.		2021-04-07 16:07:56 -07:00
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channel_route.py	Update copyright year.	2021-01-22 11:23:28 -08:00
contact.py	Update copyright year.	2021-01-22 11:23:28 -08:00
custom_cell_properties.py	Set default port map	2020-11-24 13:27:11 -08:00
custom_layer_properties.py	Remove EOL whitespace globally	2020-11-03 06:29:17 -08:00
delay_data.py	Update copyright year.	2021-01-22 11:23:28 -08:00
design.py	Merge branch 'supply_router' into dev	2021-01-25 11:01:48 -08:00
errors.py	Add exception errors file	2020-04-08 16:55:45 -07:00
geometry.py	Merge remote-tracking branch 'bvhoof/dev' into dev	2021-03-01 12:16:26 -08:00
graph_util.py	Added debug measurements along main delay paths in SRAM. WIP.	2020-11-17 12:43:17 -08:00
hierarchy_design.py	Reimplement trim options (except on unit tests).	2021-04-07 16:07:56 -07:00
hierarchy_layout.py	Merge branch 'supply_router' into dev	2021-01-25 11:01:48 -08:00
hierarchy_spice.py	Reimplement trim options (except on unit tests).	2021-04-07 16:07:56 -07:00
lef.py	Update copyright year.	2021-01-22 11:23:28 -08:00
pin_layout.py	Zoom parameter should be optional in tech files.	2021-03-02 13:38:09 -08:00
power_data.py	Update copyright year.	2021-01-22 11:23:28 -08:00
route.py	Update copyright year.	2021-01-22 11:23:28 -08:00
utils.py	Update copyright year.	2021-01-22 11:23:28 -08:00
vector.py	Update copyright year.	2021-01-22 11:23:28 -08:00
verilog.py	Update copyright year.	2021-01-22 11:23:28 -08:00
wire.py	Update copyright year.	2021-01-22 11:23:28 -08:00
wire_path.py	Update copyright year.	2021-01-22 11:23:28 -08:00
wire_spice_model.py	Update copyright year.	2021-01-22 11:23:28 -08:00