mirror of https://github.com/VLSIDA/OpenRAM.git
191 lines
7.1 KiB
Python
191 lines
7.1 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from openram import debug
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from openram.base import design, drc
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from openram.base import vector
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from openram.sram_factory import factory
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from openram.tech import layer
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from openram.tech import layer_properties as layer_props
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from openram import OPTS
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class rom_wordline_driver_array(design):
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"""
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Creates a Wordline Buffer/Inverter array
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"""
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def __init__(self, name, rows, fanout, invert_outputs=False, tap_spacing=4, flip_io=False):
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design.__init__(self, name)
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debug.info(1, "Creating {0}".format(self.name))
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self.add_comment("rows: {0} Buffer size of: {1}".format(rows, fanout))
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self.rows = rows
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self.fanout = fanout
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self.invert_outputs=invert_outputs
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self.tap_spacing = tap_spacing
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self.flip_io = flip_io
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if OPTS.tech_name == "sky130":
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self.supply_layer = "m1"
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else:
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self.supply_layer = "m2"
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_drivers()
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def create_layout(self):
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if "li" in layer:
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self.route_layer = "li"
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else:
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self.route_layer = "m1"
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self.place_drivers()
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self.route_layout()
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self.route_supplies()
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if self.tap_spacing != 0:
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self.place_taps()
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self.add_boundary()
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def add_pins(self):
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# inputs to wordline_driver.
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for i in range(self.rows):
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self.add_pin("in_{0}".format(i), "INPUT")
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# Outputs from wordline_driver.
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for i in range(self.rows):
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self.add_pin("out_{0}".format(i), "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_modules(self):
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b = factory.create(module_type="rom_base_cell")
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self.tap = factory.create(module_type="rom_poly_tap", add_tap = True)
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if self.invert_outputs:
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self.wl_driver = factory.create(module_type="pinv_dec",
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size=self.fanout,
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height=b.height,
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add_wells=False,
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flip_io=self.flip_io)
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else:
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self.wl_driver = factory.create(module_type="pbuf_dec",
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size=self.fanout,
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height=b.height,
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add_wells=False)
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def route_supplies(self):
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"""
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Add a pin for each row of vdd/gnd which
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are must-connects next level up.
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"""
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if layer_props.wordline_driver.vertical_supply:
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self.route_vertical_pins("vdd", [self], layer=self.supply_layer)
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self.route_vertical_pins("gnd", [self], layer=self.supply_layer)
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else:
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self.route_vertical_pins("vdd", self.wld_inst, xside="rx",)
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self.route_vertical_pins("gnd", self.wld_inst, xside="lx",)
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def create_drivers(self):
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self.wld_inst = []
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for row in range(self.rows):
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self.wld_inst.append(self.add_inst(name="wld{0}".format(row),
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mod=self.wl_driver))
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self.connect_inst(["in_{0}".format(row),
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"out_{0}".format(row),
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"vdd", "gnd"])
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def place_drivers(self):
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y_offset = 0
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for row in range(self.rows):
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if self.tap_spacing != 0 and row % self.tap_spacing == 0:
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y_offset += self.tap.pitch_offset
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offset = [0, y_offset]
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self.wld_inst[row].place(offset=offset)
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y_offset += self.wld_inst[row].height
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self.width = self.wl_driver.width
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self.height = self.wl_driver.height * self.rows
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def route_layout(self):
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""" Route all of the signals """
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route_width = drc["minwidth_{}".format(self.route_layer)]
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for row in range(self.rows):
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if self.flip_io:
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row_num = self.rows - row - 1
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else:
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row_num = row
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inst = self.wld_inst[row_num]
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self.copy_layout_pin(inst, "vdd")
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self.copy_layout_pin(inst, "gnd")
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self.copy_layout_pin(inst, "A", "in_{0}".format(row))
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out_pin = inst.get_pin("Z")
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# output each WL on the right
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if self.flip_io:
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wl_offset = out_pin.lc() - vector(1.6 * route_width, 0)
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else:
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wl_offset = out_pin.rc() - vector( 0.5 * route_width, 0)
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end = vector(wl_offset.x, \
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self.get_pin("in_{}".format(row)).cy() + 0.5 * route_width)
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self.add_segment_center(layer=self.route_layer,
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start=wl_offset,
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end=end)
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if self.flip_io:
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self.add_segment_center(layer=self.route_layer,
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start=out_pin.lc(),
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end=vector(wl_offset.x - 0.5 * route_width, out_pin.cy()))
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self.add_layout_pin_rect_center(text="out_{}".format(row), layer=self.route_layer, offset=end - vector(0, 0.5 * route_width))
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def place_taps(self):
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for wl in range(0 , self.rows, self.tap_spacing):
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driver = self.wld_inst[wl]
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source_pin1 = driver.get_pins("vdd")[0]
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gnd_pin1 = driver.get_pins("gnd")[0]
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left_edge = driver.get_pin("Z").cy() - 0.5 * self.contact_width - self.active_enclose_contact - self.active_space - 0.5 * self.active_contact.width
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contact_pos = vector(source_pin1.cx(), left_edge)
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self.place_tap(contact_pos, "n")
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contact_pos = vector( gnd_pin1.cx(), left_edge)
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self.place_tap(contact_pos, "p")
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if not self.invert_outputs:
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source_pin2 = driver.get_pins("vdd")[1]
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gnd_pin2 = driver.get_pins("gnd")[1]
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contact_pos = vector(source_pin2.cx(), left_edge)
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self.place_tap(contact_pos, "n")
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contact_pos = vector( gnd_pin2.cx(), left_edge)
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self.place_tap(contact_pos, "p")
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def place_tap(self, offset, well_type):
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self.add_via_center(layers=self.active_stack,
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offset=offset,
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implant_type=well_type,
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well_type=well_type,
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directions="nonpref")
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self.add_via_stack_center(offset=offset,
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from_layer=self.active_stack[2],
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to_layer=self.supply_layer)
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if well_type == "p":
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pin = "gnd"
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else:
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pin = "vdd"
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self.add_layout_pin_rect_center(text=pin, layer=self.supply_layer, offset=offset) |