mirror of https://github.com/VLSIDA/OpenRAM.git
110 lines
3.6 KiB
Python
110 lines
3.6 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from openram.base import design
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from openram.sram_factory import factory
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from openram.base import vector
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from openram.tech import layer, drc
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class rom_address_control_array(design):
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"""
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Takes the input address lines and creates the address and address bar lines for the decoder.
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Adds control logic for the precharge cycle so that all address lines are high before the read cycle
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"""
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def __init__(self, cols, inv_height=None, inv_size=1, name="", route_layer="m1"):
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self.size=inv_size
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self.cols = cols
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self.route_layer = route_layer
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dff = factory.create(module_type="dff")
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if name=="":
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name = "rom_inv_array_{0}".format(cols)
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if inv_height == None:
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self.inv_height = dff.height * 0.5
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else:
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self.inv_height = inv_height
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if "li" in layer:
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self.inv_layer = "li"
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else:
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self.inv_layer = "m1"
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super().__init__(name)
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self.create_netlist()
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self.create_layout()
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def create_netlist(self):
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self.create_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.width = self.cols * self.addr_control.width
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self.height = self.addr_control.height
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self.setup_layout_constants()
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self.place_instances()
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self.route_clk()
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self.route_sources()
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self.copy_pins()
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self.add_boundary()
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def create_modules(self):
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self.addr_control = factory.create(module_type="rom_address_control_buf", size=self.inv_height)
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def add_pins(self):
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for col in range(self.cols):
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self.add_pin("A{0}_in".format(col), "INPUT")
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for col in range(self.cols):
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self.add_pin("A{0}_out".format(col), "OUTPUT")
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for col in range(self.cols):
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self.add_pin("Abar{0}_out".format(col), "OUTPUT")
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self.add_pin("clk", "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def create_instances(self):
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self.buf_insts = []
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for col in range(self.cols):
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name = "Xaddr_buf_{0}".format(col)
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addr_buf = self.add_inst(name=name, mod=self.addr_control)
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A_in = "A{0}_in".format(col)
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Aout = "A{0}_out".format(col)
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Abar_out = "Abar{0}_out".format(col)
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self.connect_inst([A_in, Aout, Abar_out, "clk", "vdd", "gnd"])
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self.buf_insts.append(addr_buf)
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def setup_layout_constants(self):
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self.route_width = drc["minwidth_{}".format(self.route_layer)]
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def place_instances(self):
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for col in range(self.cols):
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base = vector((col+1)*(self.addr_control.width), 0)
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self.buf_insts[col].place(offset=base, mirror="MY")
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def copy_pins(self):
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for i in range(self.cols):
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self.copy_layout_pin(self.buf_insts[i], "A_out", "A{0}_out".format(i))
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self.copy_layout_pin(self.buf_insts[i], "Abar_out", "Abar{0}_out".format(i))
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self.copy_layout_pin(self.buf_insts[i], "A_in", "A{0}_in".format(i))
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def route_clk(self):
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self.route_horizontal_pins("clk", insts=self.buf_insts, layer=self.route_layer)
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def route_sources(self):
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self.route_horizontal_pins("vdd", insts=self.buf_insts, layer=self.route_layer)
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self.route_horizontal_pins("gnd", insts=self.buf_insts, layer=self.route_layer) |