mirror of https://github.com/VLSIDA/OpenRAM.git
652 lines
29 KiB
Python
652 lines
29 KiB
Python
from math import log
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import design
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from tech import drc, parameter
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import debug
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from contact import contact
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from pinv import pinv
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from nand_2 import nand_2
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from nand_3 import nand_3
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from nor_2 import nor_2
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import math
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from vector import vector
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from globals import OPTS
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class control_logic(design.design):
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"""
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Dynamically generated Control logic for the total SRAM circuit.
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"""
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def __init__(self, num_rows):
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""" Constructor """
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design.design.__init__(self, "control_logic")
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debug.info(1, "Creating {}".format(self.name))
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self.num_rows = num_rows
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self.create_layout()
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self.DRC_LVS()
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def create_layout(self):
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""" Create layout and route between modules """
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self.create_modules()
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self.setup_layout_offsets()
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self.add_modules()
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self.add_routing()
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def create_modules(self):
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""" add all the required modules """
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input_lst =["csb","web","oeb","clk"]
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output_lst = ["s_en", "w_en", "tri_en", "tri_en_bar", "clk_bar", "clk_buf"]
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rails = ["vdd", "gnd"]
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for pin in input_lst + output_lst + rails:
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self.add_pin(pin)
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self.nand2 = nand_2()
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self.add_mod(self.nand2)
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self.nand3 = nand_3()
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self.add_mod(self.nand3)
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self.nor2 = nor_2()
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self.add_mod(self.nor2)
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# Special gates: inverters for buffering
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self.inv = self.inv1 = pinv()
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self.add_mod(self.inv1)
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self.inv2 = pinv(nmos_width=2*drc["minwidth_tx"])
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self.add_mod(self.inv2)
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self.inv4 = pinv(nmos_width=4*drc["minwidth_tx"])
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self.add_mod(self.inv4)
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self.inv8 = pinv(nmos_width=8*drc["minwidth_tx"])
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self.add_mod(self.inv8)
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self.inv16 = pinv(nmos_width=16*drc["minwidth_tx"])
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self.add_mod(self.inv16)
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c = reload(__import__(OPTS.config.ms_flop_array))
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ms_flop_array = getattr(c, OPTS.config.ms_flop_array)
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self.msf_control = ms_flop_array(name="msf_control",
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columns=3,
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word_size=3)
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self.add_mod(self.msf_control)
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c = reload(__import__(OPTS.config.replica_bitline))
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replica_bitline = getattr(c, OPTS.config.replica_bitline)
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self.replica_bitline = replica_bitline(rows=int(math.ceil(self.num_rows / 10.0)))
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self.add_mod(self.replica_bitline)
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def setup_layout_offsets(self):
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""" Setup layout offsets, determine the size of the busses etc """
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# These aren't for instantiating, but we use them to get the dimensions
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self.poly_contact = contact(layer_stack=("poly", "contact", "metal1"))
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self.poly_contact_offset = vector(0.5*self.poly_contact.width,0.5*self.poly_contact.height)
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self.m1m2_via = contact(layer_stack=("metal1", "via1", "metal2"))
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self.m2m3_via = contact(layer_stack=("metal2", "via2", "metal3"))
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# For different layer width vias
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self.m1m2_offset_fix = vector(0,0.5*(drc["minwidth_metal2"]-drc["minwidth_metal1"]))
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# M1/M2 routing pitch is based on contacted pitch
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self.m1_pitch = max(self.m1m2_via.width,self.m1m2_via.height) + max(drc["metal1_to_metal1"],drc["metal2_to_metal2"])
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self.m2_pitch = max(self.m2m3_via.width,self.m2m3_via.height) + max(drc["metal2_to_metal2"],drc["metal3_to_metal3"])
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# Have the cell gap leave enough room to route an M2 wire.
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# Some cells may have pwell/nwell spacing problems too when the wells are different heights.
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self.cell_gap = max(self.m2_pitch,drc["pwell_to_nwell"])
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# Amount to shift a 90 degree rotated via from center-line path routing to it's offset
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self.m1m2_via_offset = vector(self.m1m2_via.first_layer_height,-0.5*drc["minwidth_metal2"])
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self.m2m3_via_offset = vector(self.m2m3_via.first_layer_height,-0.5*drc["minwidth_metal3"])
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# First RAIL Parameters: gnd, oe, oebar, cs, we, clk_buf, clk_bar
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self.rail_1_start_x = 0
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self.num_rails_1 = 8
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self.rail_1_names = ["clk_buf", "gnd", "oe_bar", "cs", "we", "vdd", "oe", "clk_bar"]
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self.overall_rail_1_gap = (self.num_rails_1 + 2) * self.m2_pitch
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self.rail_1_x_offsets = {}
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# Second RAIL Parameters: vdd
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self.rail_2_start_x = 0
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self.num_rails_2 = 0
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self.rail_2_names = ["vdd"]
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self.overall_rail_2_gap = (self.num_rails_2 + 2) * self.m2_pitch
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self.rail_2_x_offsets = {}
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# GAP between main control and replica bitline
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self.replica_bitline_gap = 2*self.m2_pitch
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def add_modules(self):
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""" Place all the modules """
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self.add_control_flops()
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self.add_clk_buffer(0)
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self.add_1st_row(0)
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self.add_2nd_row(self.inv1.height)
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self.add_3rd_row(2*self.inv1.height)
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self.add_control_routing()
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self.add_rbl(0)
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self.add_layout_pins()
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self.add_lvs_correspondence_points()
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self.height = max(self.replica_bitline.width, 3 * self.inv1.height, self.msf_offset.y)
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self.width = self.replica_bitline_offset.x + self.replica_bitline.height
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def add_routing(self):
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""" Routing between modules """
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self.add_clk_routing()
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self.add_trien_routing()
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self.add_rblk_routing()
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self.add_wen_routing()
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self.add_sen_routing()
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self.add_output_routing()
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self.add_supply_routing()
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def add_control_flops(self):
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""" Add the control signal flops for OEb, WEb, CSb. """
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self.msf_offset = vector(0, self.inv.height+self.msf_control.width+2*self.m2_pitch)
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self.msf_inst=self.add_inst(name="msf_control",
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mod=self.msf_control,
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offset=self.msf_offset,
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rotate=270)
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# don't change this order. This pins are meant for internal connection of msf array inside the control logic.
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# These pins are connecting the msf_array inside of control_logic.
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temp = ["oeb", "csb", "web",
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"oe_bar", "oe",
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"cs_bar", "cs",
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"we_bar", "we",
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"clk_buf", "vdd", "gnd"]
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self.connect_inst(temp)
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def add_rbl(self,y_off):
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""" Add the replica bitline """
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self.replica_bitline_offset = vector(self.rail_2_end_x , y_off)
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self.rbl=self.add_inst(name="replica_bitline",
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mod=self.replica_bitline,
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offset=self.replica_bitline_offset,
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mirror="MX",
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rotate=90)
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self.connect_inst(["rblk", "pre_s_en", "vdd", "gnd"])
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def add_layout_pins(self):
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""" Add the input/output layout pins. """
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# Top to bottom: CS WE OE signal groups
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pin_set = ["oeb","csb","web"]
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for (i,pin_name) in zip(range(3),pin_set):
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subpin_name="din[{}]".format(i)
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pins=self.msf_inst.get_pins(subpin_name)
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for pin in pins:
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if pin.layer=="metal3":
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self.add_layout_pin(text=pin_name,
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layer="metal3",
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offset=pin.ll(),
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width=pin.width(),
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height=pin.height())
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pin=self.clk_inv1.get_pin("A")
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self.add_layout_pin(text="clk",
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layer="metal1",
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offset=pin.ll())
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pin=self.clk_inv1.get_pin("gnd")
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self.add_layout_pin(text="gnd",
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layer="metal1",
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offset=pin.ll(),
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width=self.width)
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pin=self.clk_inv1.get_pin("vdd")
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self.add_layout_pin(text="vdd",
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layer="metal1",
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offset=pin.ll(),
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width=self.width)
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def add_clk_buffer(self,y_off):
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""" Add the multistage clock buffer below the control flops """
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# 4 stage clock buffer
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self.clk_inv1_offset = vector(0, y_off)
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self.clk_inv1=self.add_inst(name="inv_clk1_bar",
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mod=self.inv2,
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offset=self.clk_inv1_offset)
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self.connect_inst(["clk", "clk1_bar", "vdd", "gnd"])
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self.clk_inv2_offset = self.clk_inv1_offset + vector(self.inv2.width,0)
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self.clk_inv2=self.add_inst(name="inv_clk2",
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mod=self.inv4,
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offset=self.clk_inv2_offset)
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self.connect_inst(["clk1_bar", "clk2", "vdd", "gnd"])
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self.clk_bar_offset = self.clk_inv2_offset + vector(self.inv4.width,0)
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self.clk_bar=self.add_inst(name="inv_clk_bar",
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mod=self.inv8,
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offset=self.clk_bar_offset)
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self.connect_inst(["clk2", "clk_bar", "vdd", "gnd"])
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self.clk_buf_offset = self.clk_bar_offset + vector(self.inv8.width,0)
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self.clk_buf=self.add_inst(name="inv_clk_buf",
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mod=self.inv16,
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offset=self.clk_buf_offset)
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self.connect_inst(["clk_bar", "clk_buf", "vdd", "gnd"])
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# This is the first rail offset
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self.rail_1_start_x = max(self.msf_offset.x + self.msf_control.height,self.clk_buf_offset.x+self.inv16.width)
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def add_1st_row(self,y_off):
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x_off = self.rail_1_start_x + self.overall_rail_1_gap
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# input: OE, clk_bar,CS output: rblk_bar
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self.rblk_bar_offset = vector(x_off, y_off)
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self.rblk_bar=self.add_inst(name="nand3_rblk_bar",
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mod=self.nand3,
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offset=self.rblk_bar_offset)
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self.connect_inst(["clk_bar", "oe", "cs", "rblk_bar", "vdd", "gnd"])
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x_off += self.nand3.width
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# input: rblk_bar, output: rblk
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self.rblk_offset = vector(x_off, y_off)
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self.rblk=self.add_inst(name="inv_rblk",
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mod=self.inv1,
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offset=self.rblk_offset)
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self.connect_inst(["rblk_bar", "rblk", "vdd", "gnd"])
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#x_off += self.inv1.width
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self.row_1_width = x_off
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def add_2nd_row(self, y_off):
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# start after first rails
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x_off = self.rail_1_start_x + self.overall_rail_1_gap
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y_off += self.inv1.height
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# input: clk_buf, OE_bar output: tri_en
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self.tri_en_offset = vector(x_off, y_off)
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self.tri_en=self.add_inst(name="nor2_tri_en",
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mod=self.nor2,
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offset=self.tri_en_offset,
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mirror="MX")
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self.connect_inst(["clk_buf", "oe_bar", "tri_en", "vdd", "gnd"])
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x_off += self.nor2.width + self.cell_gap
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# input: OE, clk_bar output: tri_en_bar
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self.tri_en_bar_offset = vector(x_off,y_off)
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self.tri_en_bar=self.add_inst(name="nand2_tri_en",
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mod=self.nand2,
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offset=self.tri_en_bar_offset,
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mirror="MX")
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self.connect_inst(["oe", "clk_bar", "tri_en_bar", "vdd", "gnd"])
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x_off += self.nand2.width
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x_off += self.inv1.width + self.cell_gap
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# BUFFER INVERTERS FOR S_EN
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# input: input: pre_s_en_bar, output: s_en
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self.s_en_offset = vector(x_off, y_off)
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self.s_en=self.add_inst(name="inv_s_en",
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mod=self.inv1,
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offset=self.s_en_offset,
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mirror="XY")
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self.connect_inst(["pre_s_en_bar", "s_en", "vdd", "gnd"])
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x_off += self.inv1.width
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# input: pre_s_en, output: pre_s_en_bar
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self.pre_s_en_bar_offset = vector(x_off, y_off)
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self.pre_s_en_bar=self.add_inst(name="inv_pre_s_en_bar",
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mod=self.inv1,
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offset=self.pre_s_en_bar_offset,
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mirror="XY")
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self.connect_inst(["pre_s_en", "pre_s_en_bar", "vdd", "gnd"])
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#x_off += self.inv1.width
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self.row_2_width = x_off
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def add_3rd_row(self, y_off):
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# start after first rails
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x_off = self.rail_1_start_x + self.overall_rail_1_gap
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# This prevents some M2 outputs from overlapping (hack)
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x_off += self.inv1.width
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# input: WE, clk_bar, CS output: w_en_bar
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self.w_en_bar_offset = vector(x_off, y_off)
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self.w_en_bar=self.add_inst(name="nand3_w_en_bar",
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mod=self.nand3,
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offset=self.w_en_bar_offset)
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self.connect_inst(["clk_bar", "we", "cs", "w_en_bar", "vdd", "gnd"])
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x_off += self.nand3.width
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# input: w_en_bar, output: pre_w_en
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self.pre_w_en_offset = vector(x_off, y_off)
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self.pre_w_en=self.add_inst(name="inv_pre_w_en",
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mod=self.inv1,
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offset=self.pre_w_en_offset)
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self.connect_inst(["w_en_bar", "pre_w_en", "vdd", "gnd"])
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x_off += self.inv1.width
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# BUFFER INVERTERS FOR W_EN
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self.pre_w_en_bar_offset = vector(x_off, y_off)
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self.pre_w_en_bar=self.add_inst(name="inv_pre_w_en_bar",
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mod=self.inv1,
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offset=self.pre_w_en_bar_offset)
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self.connect_inst(["pre_w_en", "pre_w_en_bar", "vdd", "gnd"])
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x_off += self.inv1.width
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self.w_en_offset = vector(x_off, y_off)
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self.w_en=self.add_inst(name="inv_w_en2",
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mod=self.inv1,
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offset=self.w_en_offset)
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self.connect_inst(["pre_w_en_bar", "w_en", "vdd", "gnd"])
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#x_off += self.inv1.width
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self.row_3_width = x_off
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def add_control_routing(self):
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""" Route the vertical rails for internal control signals """
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control_rail_height = max(3 * self.inv1.height, self.msf_offset.y)
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for i in range(self.num_rails_1):
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offset = vector(self.rail_1_start_x + (i+1) * self.m2_pitch,0)
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if self.rail_1_names[i] in ["clk_buf", "clk_bar", "vdd", "gnd"]:
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self.add_layout_pin(text=self.rail_1_names[i],
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layer="metal2",
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offset=offset,
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width=drc["minwidth_metal2"],
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height=control_rail_height)
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else:
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# just for LVS correspondence...
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self.add_label_pin(text=self.rail_1_names[i],
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layer="metal2",
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offset=offset,
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width=drc["minwidth_metal2"],
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height=control_rail_height)
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self.rail_1_x_offsets[self.rail_1_names[i]]=offset.x + 0.5*drc["minwidth_metal2"] # center offset
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# pins are in order ["oeb","csb","web"] # 0 1 2
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self.connect_rail_from_left_m2m3(self.msf_inst,"dout_bar[0]","oe")
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self.connect_rail_from_left_m2m3(self.msf_inst,"dout[0]","oe_bar")
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self.connect_rail_from_left_m2m3(self.msf_inst,"dout_bar[1]","cs")
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self.connect_rail_from_left_m2m3(self.msf_inst,"dout_bar[2]","we")
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# Connect the gnd and vdd of the control
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gnd_pins = self.msf_inst.get_pins("gnd")
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for p in gnd_pins:
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if p.layer != "metal2":
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continue
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gnd_pin = p.rc()
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gnd_rail_position = vector(self.rail_1_x_offsets["gnd"], gnd_pin.y)
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self.add_wire(("metal3","via2","metal2"),[gnd_pin, gnd_rail_position, gnd_rail_position - vector(0,self.m2_pitch)])
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self.add_via(layers=("metal2","via2","metal3"),
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offset=gnd_pin + self.m2m3_via_offset,
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rotate=90)
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vdd_pins = self.msf_inst.get_pins("vdd")
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for p in vdd_pins:
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if p.layer != "metal1":
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continue
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clk_vdd_position = vector(p.bc().x,self.clk_buf.get_pin("vdd").uy())
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self.add_path("metal1",[p.bc(),clk_vdd_position])
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self.rail_2_start_x = max (self.row_1_width, self.row_2_width, self.row_3_width)
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for i in range(self.num_rails_2):
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offset = vector(self.rail_2_start_x + i * self.m1_pitch, 0)
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self.add_rect(layer="metal1",
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offset=offset,
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width=drc["minwidth_metal1"],
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height=self.logic_height)
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self.rail_2_x_offsets[self.rail_2_names[i]]=offset.x + 0.5*drc["minwidth_metal1"] # center offset
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self.rail_2_end_x = self.rail_2_start_x + (self.num_rails_2+1) * self.m2_pitch
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def add_rblk_routing(self):
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""" Connect the logic for the rblk generation """
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self.connect_rail_from_right(self.rblk_bar,"A","clk_bar")
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self.connect_rail_from_right(self.rblk_bar,"B","oe")
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self.connect_rail_from_right(self.rblk_bar,"C","cs")
|
|
|
|
# Connect the NAND3 output to the inverter
|
|
# The pins are assumed to extend all the way to the cell edge
|
|
rblk_bar_pin = self.rblk_bar.get_pin("Z").ur()
|
|
inv_in_pin = self.rblk.get_pin("A").ll()
|
|
mid1 = vector(inv_in_pin.x,rblk_bar_pin.y)
|
|
self.add_path("metal1",[rblk_bar_pin,mid1,inv_in_pin])
|
|
|
|
# Connect the output to the RBL
|
|
rblk_pin = self.rblk.get_pin("Z").rc()
|
|
rbl_in_pin = self.rbl.get_pin("en").lc()
|
|
mid1 = vector(rblk_pin.x,rbl_in_pin.y)
|
|
self.add_path("metal1",[rblk_pin,mid1,rbl_in_pin])
|
|
|
|
def connect_rail_from_right(self,inst, pin, rail):
|
|
""" Helper routine to connect an unrotated/mirrored oriented instance to the rails """
|
|
in_pin = inst.get_pin(pin).lc()
|
|
rail_position = vector(self.rail_1_x_offsets[rail], in_pin.y)
|
|
self.add_wire(("metal1","via1","metal2"),[in_pin, rail_position, rail_position - vector(0,self.m2_pitch)])
|
|
|
|
def connect_rail_from_right_m2m3(self,inst, pin, rail):
|
|
""" Helper routine to connect an unrotated/mirrored oriented instance to the rails """
|
|
in_pin = inst.get_pin(pin).lc()
|
|
rail_position = vector(self.rail_1_x_offsets[rail], in_pin.y)
|
|
self.add_wire(("metal3","via2","metal2"),[in_pin, rail_position, rail_position - vector(0,self.m2_pitch)])
|
|
# Bring it up to M2 for M2/M3 routing
|
|
self.add_via(layers=("metal1","via1","metal2"),
|
|
offset=in_pin + self.m1m2_via_offset,
|
|
rotate=90)
|
|
self.add_via(layers=("metal2","via2","metal3"),
|
|
offset=in_pin + self.m2m3_via_offset,
|
|
rotate=90)
|
|
|
|
|
|
def connect_rail_from_left(self,inst, pin, rail):
|
|
""" Helper routine to connect an unrotated/mirrored oriented instance to the rails """
|
|
in_pin = inst.get_pin(pin).rc()
|
|
rail_position = vector(self.rail_1_x_offsets[rail], in_pin.y)
|
|
self.add_wire(("metal1","via1","metal2"),[in_pin, rail_position, rail_position - vector(0,self.m2_pitch)])
|
|
self.add_via(layers=("metal1","via1","metal2"),
|
|
offset=in_pin + self.m1m2_via_offset,
|
|
rotate=90)
|
|
|
|
def connect_rail_from_left_m2m3(self,inst, pin, rail):
|
|
""" Helper routine to connect an unrotated/mirrored oriented instance to the rails """
|
|
in_pin = inst.get_pin(pin).rc()
|
|
rail_position = vector(self.rail_1_x_offsets[rail], in_pin.y)
|
|
self.add_wire(("metal3","via2","metal2"),[in_pin, rail_position, rail_position - vector(0,self.m2_pitch)])
|
|
# This via is needed for clk_bar, but is extraneous for the output signals
|
|
self.add_via(layers=("metal1","via1","metal2"),
|
|
offset=in_pin + self.m1m2_via_offset,
|
|
rotate=90)
|
|
self.add_via(layers=("metal2","via2","metal3"),
|
|
offset=in_pin + self.m2m3_via_offset,
|
|
rotate=90)
|
|
|
|
|
|
def add_wen_routing(self):
|
|
self.connect_rail_from_right(self.w_en_bar,"A","clk_bar")
|
|
self.connect_rail_from_right(self.w_en_bar,"B","we")
|
|
self.connect_rail_from_right(self.w_en_bar,"C","cs")
|
|
|
|
# Connect the NAND3 output to the inverter
|
|
# The pins are assumed to extend all the way to the cell edge
|
|
w_en_bar_pin = self.w_en_bar.get_pin("Z").ur()
|
|
inv_in_pin = self.pre_w_en.get_pin("A").ll()
|
|
mid1 = vector(inv_in_pin.x,w_en_bar_pin.y)
|
|
self.add_path("metal1",[w_en_bar_pin,mid1,inv_in_pin])
|
|
|
|
|
|
|
|
def add_trien_routing(self):
|
|
self.connect_rail_from_right(self.tri_en,"A","clk_buf")
|
|
self.connect_rail_from_right(self.tri_en,"B","oe_bar")
|
|
|
|
self.connect_rail_from_right_m2m3(self.tri_en_bar,"A","clk_bar")
|
|
self.connect_rail_from_right_m2m3(self.tri_en_bar,"B","oe")
|
|
|
|
|
|
|
|
|
|
def add_sen_routing(self):
|
|
rbl_out_pin = self.rbl.get_pin("out").ul()
|
|
in_pin = self.pre_s_en_bar.get_pin("A").rc()
|
|
mid1 = vector(rbl_out_pin.x,in_pin.y)
|
|
self.add_path("metal1",[rbl_out_pin,mid1,in_pin])
|
|
#s_en_pin = self.s_en.get_pin("Z").lc()
|
|
|
|
|
|
def add_clk_routing(self):
|
|
""" Route the clk and clk_bar signal internally """
|
|
|
|
# clk_buf
|
|
clk_buf_pin = self.clk_buf.get_pin("Z").rc()
|
|
clk_buf_rail_position = vector(self.rail_1_x_offsets["clk_buf"], clk_buf_pin.y)
|
|
self.add_wire(("metal1","via1","metal2"),[clk_buf_pin, clk_buf_rail_position, clk_buf_rail_position - vector(0,self.m2_pitch)])
|
|
|
|
# clk_bar
|
|
self.connect_rail_from_left_m2m3(self.clk_bar,"Z","clk_bar")
|
|
|
|
# clk_buf to msf control flops
|
|
msf_clk_pin = self.msf_inst.get_pin("clk").bc()
|
|
mid1 = msf_clk_pin - vector(0,self.m2_pitch)
|
|
clk_buf_rail_position = vector(self.rail_1_x_offsets["clk_buf"], mid1.y)
|
|
# route on M2 to allow vdd connection
|
|
self.add_wire(("metal2","via1","metal1"),[msf_clk_pin, mid1, clk_buf_rail_position])
|
|
|
|
def connect_right_pin_to_output_pin(self, inst, pin_name, out_name):
|
|
""" Create an output pin on the bottom side from the pin of a given instance. """
|
|
out_pin = inst.get_pin(pin_name).ur()
|
|
self.add_via(layers=("metal1","via1","metal2"),
|
|
offset=out_pin + vector(self.m1m2_via.height,-self.m1m2_via.first_layer_width) - self.m1m2_offset_fix,
|
|
rotate=90)
|
|
self.add_layout_pin(text=out_name,
|
|
layer="metal2",
|
|
offset=out_pin.scale(1,0),
|
|
height=out_pin.y)
|
|
|
|
def connect_left_pin_to_output_pin(self, inst, pin_name, out_name):
|
|
""" Create an output pin on the bottom side from the pin of a given instance. """
|
|
out_pin = inst.get_pin(pin_name).ul()
|
|
self.add_via(layers=("metal1","via1","metal2"),
|
|
offset=out_pin + vector(self.m1m2_via.height,-self.m1m2_via.first_layer_width) - self.m1m2_offset_fix,
|
|
rotate=90)
|
|
self.add_layout_pin(text=out_name,
|
|
layer="metal2",
|
|
offset=out_pin.scale(1,0),
|
|
height=out_pin.y)
|
|
|
|
def add_output_routing(self):
|
|
""" Output pin routing """
|
|
self.connect_right_pin_to_output_pin(self.tri_en, "Z", "tri_en")
|
|
self.connect_right_pin_to_output_pin(self.tri_en_bar, "Z", "tri_en_bar")
|
|
self.connect_right_pin_to_output_pin(self.w_en, "Z", "w_en")
|
|
self.connect_left_pin_to_output_pin(self.s_en, "Z", "s_en")
|
|
|
|
def add_supply_routing(self):
|
|
|
|
rows_start = self.rail_1_start_x + self.overall_rail_1_gap
|
|
rows_end = max(self.row_1_width,self.row_2_width,self.row_3_width)
|
|
vdd_rail_position = vector(self.rail_1_x_offsets["vdd"], 0)
|
|
well_width = drc["minwidth_well"]
|
|
|
|
# M1 gnd rail from inv1 to max
|
|
start_offset = self.clk_inv1.get_pin("gnd").lc()
|
|
row1_gnd_end_offset = vector(rows_end,start_offset.y)
|
|
self.add_path("metal1",[start_offset,row1_gnd_end_offset])
|
|
rail_position = vector(self.rail_1_x_offsets["gnd"], start_offset.y)
|
|
self.add_wire(("metal1","via1","metal2"),[vector(rows_start,start_offset.y), rail_position, rail_position + vector(0,self.m2_pitch)])
|
|
|
|
# also add a well + around the rail
|
|
self.add_rect(layer="pwell",
|
|
offset=vector(rows_start,start_offset.y),
|
|
width=rows_end-rows_start,
|
|
height=well_width)
|
|
self.add_rect(layer="vtg",
|
|
offset=vector(rows_start,start_offset.y),
|
|
width=rows_end-rows_start,
|
|
height=well_width)
|
|
|
|
# M1 vdd rail from inv1 to max
|
|
start_offset = self.clk_inv1.get_pin("vdd").lc()
|
|
row1_vdd_end_offset = vector(rows_end,start_offset.y)
|
|
self.add_path("metal1",[start_offset,row1_vdd_end_offset])
|
|
rail_position = vector(self.rail_1_x_offsets["vdd"], start_offset.y)
|
|
self.add_wire(("metal1","via1","metal2"),[vector(rows_start,start_offset.y), rail_position, rail_position - vector(0,self.m2_pitch)])
|
|
|
|
# also add a well +- around the rail
|
|
self.add_rect(layer="nwell",
|
|
offset=vector(rows_start,start_offset.y)-vector(0,0.5*well_width),
|
|
width=rows_end-rows_start,
|
|
height=well_width)
|
|
self.add_rect(layer="vtg",
|
|
offset=vector(rows_start,start_offset.y)-vector(0,0.5*well_width),
|
|
width=rows_end-rows_start,
|
|
height=well_width)
|
|
|
|
|
|
# M1 gnd rail from inv1 to max
|
|
start_offset = vector(rows_start, self.tri_en.get_pin("gnd").lc().y)
|
|
row3_gnd_end_offset = vector(rows_end,start_offset.y)
|
|
self.add_path("metal1",[start_offset,row3_gnd_end_offset])
|
|
rail_position = vector(self.rail_1_x_offsets["gnd"], start_offset.y)
|
|
self.add_wire(("metal1","via1","metal2"),[vector(rows_start,start_offset.y), rail_position, rail_position - vector(0,self.m2_pitch)])
|
|
|
|
# also add a well +- around the rail
|
|
self.add_rect(layer="pwell",
|
|
offset=vector(rows_start,start_offset.y)-vector(0,0.5*well_width),
|
|
width=rows_end-rows_start,
|
|
height=well_width)
|
|
self.add_rect(layer="vtg",
|
|
offset=vector(rows_start,start_offset.y)-vector(0,0.5*well_width),
|
|
width=rows_end-rows_start,
|
|
height=well_width)
|
|
|
|
|
|
# M1 vdd rail from inv1 to max
|
|
start_offset = vector(rows_start, self.w_en_bar.get_pin("vdd").lc().y)
|
|
row3_vdd_end_offset = vector(rows_end,start_offset.y)
|
|
self.add_path("metal1",[start_offset,row3_vdd_end_offset])
|
|
rail_position = vector(self.rail_1_x_offsets["vdd"], start_offset.y)
|
|
self.add_wire(("metal1","via1","metal2"),[vector(rows_start,start_offset.y), rail_position, rail_position - vector(0,self.m2_pitch)])
|
|
|
|
|
|
# Now connect the vdd and gnd rails between the replica bitline and the control logic
|
|
(rbl_row3_gnd,rbl_row1_gnd) = self.rbl.get_pins("gnd")
|
|
(rbl_row3_vdd,rbl_row1_vdd) = self.rbl.get_pins("vdd")
|
|
|
|
self.add_path("metal1",[row1_gnd_end_offset,rbl_row1_gnd.lc()])
|
|
self.add_path("metal1",[row1_vdd_end_offset,rbl_row1_vdd.lc()])
|
|
self.add_path("metal1",[row3_gnd_end_offset,rbl_row3_gnd.lc()])
|
|
# row 3 may have a jog due to unequal row heights, so force the full overlap at the end
|
|
self.add_path("metal1",[row3_vdd_end_offset - vector(self.m1_pitch,0),row3_vdd_end_offset,rbl_row3_vdd.lc()])
|
|
|
|
|
|
# also add a well - around the rail
|
|
self.add_rect(layer="nwell",
|
|
offset=vector(rows_start,start_offset.y)-vector(0,well_width),
|
|
width=rows_end-rows_start,
|
|
height=well_width)
|
|
self.add_rect(layer="vtg",
|
|
offset=vector(rows_start,start_offset.y)-vector(0,well_width),
|
|
width=rows_end-rows_start,
|
|
height=well_width)
|
|
|
|
|
|
def add_lvs_correspondence_points(self):
|
|
""" This adds some points for easier debugging if LVS goes wrong.
|
|
These should probably be turned off by default though, since extraction
|
|
will show these as ports in the extracted netlist.
|
|
"""
|
|
pin=self.clk_inv1.get_pin("Z")
|
|
self.add_label_pin(text="clk1_bar",
|
|
layer="metal1",
|
|
offset=pin.ll(),
|
|
height=pin.height(),
|
|
width=pin.width())
|
|
|
|
pin=self.clk_inv2.get_pin("Z")
|
|
self.add_label_pin(text="clk2",
|
|
layer="metal1",
|
|
offset=pin.ll(),
|
|
height=pin.height(),
|
|
width=pin.width())
|
|
|
|
|