mirror of https://github.com/VLSIDA/OpenRAM.git
49 lines
1.5 KiB
Python
Executable File
49 lines
1.5 KiB
Python
Executable File
#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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#Copyright (c) 2016-2019 Regents of the University of California and The Board
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#of Regents for the Oklahoma Agricultural and Mechanical College
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#(acting for and on behalf of Oklahoma State University)
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#All rights reserved.
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#
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"""
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Run a test on a replica bitline
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"""
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import unittest
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from testutils import header,openram_test
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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from sram_factory import factory
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import debug
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class replica_bitline_test(openram_test):
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def runTest(self):
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globals.init_openram("config_{0}".format(OPTS.tech_name))
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# check replica bitline in single port
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stages=4
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fanout=4
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rows=13
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debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
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a = factory.create(module_type="replica_bitline", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
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self.local_check(a)
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stages=8
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rows=100
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debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
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a = factory.create(module_type="replica_bitline", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
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self.local_check(a)
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globals.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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