mirror of https://github.com/VLSIDA/OpenRAM.git
59 lines
2.0 KiB
Python
Executable File
59 lines
2.0 KiB
Python
Executable File
#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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#Copyright (c) 2016-2019 Regents of the University of California and The Board
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#of Regents for the Oklahoma Agricultural and Mechanical College
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#(acting for and on behalf of Oklahoma State University)
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#All rights reserved.
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#
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"""
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Run a regression test on a precharge array
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"""
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import unittest
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from testutils import header,openram_test
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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from sram_factory import factory
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import debug
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class precharge_test(openram_test):
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def runTest(self):
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globals.init_openram("config_{0}".format(OPTS.tech_name))
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# check precharge array in single port
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debug.info(2, "Checking 3 column precharge")
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pc = factory.create(module_type="precharge_array", columns=3)
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self.local_check(pc)
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# check precharge array in multi-port
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OPTS.bitcell = "bitcell_1rw_1r"
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OPTS.num_rw_ports = 1
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OPTS.num_r_ports = 1
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OPTS.num_w_ports = 0
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factory.reset()
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debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell")
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pc = factory.create(module_type="precharge_array", columns=3, bitcell_bl="bl0", bitcell_br="br0")
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self.local_check(pc)
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# debug.info(2, "Checking 3 column precharge array for pbitcell (innermost connections)")
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# pc = precharge_array.precharge_array(name="pre3", columns=3, bitcell_bl="bl0", bitcell_br="br0")
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# self.local_check(pc)
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# debug.info(2, "Checking 3 column precharge array for pbitcell (outermost connections)")
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# pc = precharge_array.precharge_array(name="pre4", columns=3, bitcell_bl="bl2", bitcell_br="br2")
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# self.local_check(pc)
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globals.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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